Graphical programs with FIFO structure for controller/FPGA communications

1. A computer-implemented method for communicating between programs executing respectively on a controller and a programmable hardware element, the method comprising:

creating a first graphical program in response to first user input, wherein the first graphical program comprises a first plurality of interconnected nodes that visually indicate functionality of the first graphical program, wherein the first graphical program includes a first node that represents a first in first out (FIFO) structure;

creating a second graphical program in response to second user input, wherein the second graphical program comprises a second plurality of interconnected nodes that visually indicate functionality of the second graphical program, wherein the second graphical program includes a second node that provides an interface to the FIFO structure;

deploying the first graphical program to the programmable hardware element;

configuring at least a portion of the FIFO structure on the programmable hardware element;

deploying the second graphical program to the controller;

wherein the first graphical program and the second graphical program are executable to communicate via the FIFO structure to cooperatively perform a specified task.

2. The method of claim 1 , the method further comprising:

automatically generating at least a portion of data transfer logic in response to said including the first node and in accordance with configuration information for the FIFO structure, wherein the at least a portion of data transfer logic is deployable to the programmable hardware element to implement data transfer functionality for the FIFO structure.

3. The method of claim 2 , further comprising:

deploying the at least a portion of data transfer logic to the programmable hardware element, wherein said executing the first graphical program on the programmable hardware element further comprises executing the at least a portion of the data transfer logic to facilitate communications between the first and second graphical programs.

4. The method of claim 2 ,

wherein the FIFO structure is a Direct Memory Access (DMA) FIFO; and

wherein the data transfer logic comprises DMA logic.

5. The method of claim 4 , wherein the DMA logic comprises at least a portion of a DMA controller.

6. The method of claim 1 , wherein data are transferred between the first and second graphical programs via program instructions executed by the controller.

7. The method of claim 6 , wherein the data are transferred between the first and second graphical programs via program instructions executed by the controller using one or more of:

programmed I/O; or

interrupt-driven I/O.

8. The method of claim 1 , wherein said deploying the first graphical program to the programmable hardware element comprises:

generating a hardware configuration program based on the first graphical program; and

deploying the hardware configuration program on the programmable hardware element.

9. The method of claim 8 , wherein the first node is configurable to specify one or more of:

depth of the FIFO structure;

direction of the FIFO structure, comprising one of:

controller memory to programmable hardware element; and

programmable hardware element to controller memory; and

data type of the FIFO structure.

10. The method of claim 9 , wherein the depth of the FIFO structure comprises:

a hardware depth, comprising a depth of the first portion of the FIFO structure;

a memory depth, comprising a depth of the second portion of the FIFO structure; and

wherein the depth comprises the sum of the hardware depth and the memory depth.

11. The method of claim 10 ,

wherein the hardware depth of the FIFO structure is configurable at compile time; and

wherein the memory depth of the FIFO structure is configurable at run time.

12. The method of claim 9 ,

wherein the FIFO structure comprises a front, from which data may be read, and a rear, to which data may be written; and

wherein, if the direction of the FIFO structure is configured to be memory to programmable hardware element, the first portion of the FIFO structure includes the front of the FIFO structure and the second portion of the FIFO structure includes the rear of the FIFO structure , and if the direction of the FIFO structure is configured to be programmable hardware element to memory, the first portion of the FIFO structure includes the rear of the FIFO structure and the second portion of the FIFO structure includes the front of the FIFO structure.

13. The method of claim 1 , wherein the second node is configurable to specify a desired function of the FIFO structure.

14. The method of claim 13 , wherein the desired function of the FIFO structure comprises one or more of:

read operations;

write operations;

start operations;

stop operations; and

configure operations.

15. The method of claim 14 , wherein said specifying a desired function of the FIFO structure comprises:

providing one or more selectable options for specifying the desired function of the FIFO structure; and

receiving input selecting one of the one or more selectable options to specify the desired function of the FIFO structure;

wherein, after said selecting, the second node is executable to invoke the desired function of the FIFO structure.

16. The method of claim 15 ,

wherein at least one of the one or more selectable options specifies a first function that requires one or more corollary functions; and

wherein, if the second node is configured to invoke the first function, the second node is executable to automatically invoke the one or more corollary functions in addition to the first function.

17. The method of claim 15 , wherein providing the one or more selectable options for specifying the desired function of the FIFO structure comprises:

determining the FIFO structure's configuration; and

providing only options that are in accordance with the FIFO structures's configuration.

18. The method of claim 17 , wherein said determining the FIFO structure's configuration comprises one or more of:

edit time source code of the first node; and

a compiled bit file generated from the source code of the first node.

19. The method of claim 17 , wherein said determining the FIFO structure's configuration is performed by one or more of:

edit time code for the second node;

program code associated with the second node; and

a development environment of the second graphical program.

20. The method of claim 13 , wherein the second graphical program includes one or more additional second nodes, each operable to provide a respective additional controller interface to the FIFO structure, and wherein each additional second node is configurable to specify a respective desired function of the FIFO structure;

wherein, after being configured, each additional second node is executable to invoke the respective desired function of the FIFO structure.

21. The method of claim 1 , further comprising:

configuring at least a portion of the FIFO structure on the controller.

22. A non-transitory memory medium that stores program instructions for communicating between programs executing respectively on a controller and a programmable hardware element, wherein the program instructions are computer-executable to perform:

creating a first graphical program in response to first user input, wherein the first graphical program comprises a first plurality of interconnected nodes that visually indicate functionality of the first graphical program, wherein the first graphical program includes a first node that represents a first in first out (FIFO) structure;

creating a second graphical program in response to second user input, wherein the second graphical program comprises a second plurality of interconnected nodes that visually indicate functionality of the second graphical program, wherein the second graphical program includes a second node that provides an interface to the FIFO structure;

deploying the first graphical program to the programmable hardware element;

deploying the second graphical program to the controller;

wherein the first graphical program and the second graphical program are executable to communicate via the FIFO structure to cooperatively perform a specified task.

23. The non-transitory memory medium of claim 22 , wherein the program instructions are further computer-executable to perform:

automatically generating at least a portion of data transfer logic in response to said including the first node and in accordance with configuration information for the FIFO structure; and

deploying the at least a portion of data transfer logic to the programmable hardware element to implement data transfer functionality for the FIFO structure.

24. The non-transitory memory medium of claim 23 ,

wherein the FIFO structure is a Direct Memory Access (DMA) FIFO; and

wherein the data transfer logic comprises DMA logic.

25. The non-transitory memory medium of claim 24 , wherein the DMA logic comprises at least a portion of a DMA controller.

26. The non-transitory memory medium of claim 22 , wherein data are transferred between the first and second graphical programs via program instructions executed by the controller.

27. The non-transitory memory medium of claim 26 , wherein the data are transferred between the first and second graphical programs via program instructions executed by the controller using one or more of:

programmed I/O; or

interrupt-driven I/O.

28. The non-transitory memory medium of claim 22 , wherein said deploying the first graphical program to the programmable hardware element comprises:

generating a hardware configuration program based on the first graphical program; and

deploying the hardware configuration program on the programmable hardware element.

29. A system for communicating between programs executing respectively on a controller and a programmable hardware element, the system comprising:

a first node representing a FIFO structure, wherein a first portion of the FIFO structure is operable to be implemented on the programmable hardware element, wherein a second portion of the FIFO structure is operable to be implemented in memory of the controller, wherein the first node is operable to be included in a first graphical program comprising a first plurality of interconnected nodes that visually indicate functionality of the first graphical program; and

a second node operable to provide a controller interface to the FIFO structure, wherein the second node is operable to be included in a second graphical program comprising a second plurality of interconnected nodes that visually indicate functionality of the second graphical program;

wherein the first graphical program, including the first node, is deployable to the programmable hardware element, wherein the second graphical program, including the second node, is deployable to the controller, and wherein the first and the second graphical program are executable to communicate via the FIFO structure to cooperatively perform a specified task.

30. The system of claim 29 , wherein the first node is configurable to specify one or more of:

depth of the FIFO structure;

direction of the FIFO structure, comprising one of:

controller memory to programmable hardware element; and

programmable hardware element to controller memory; and

data type of the FIFO structure.

31. The system of claim 30 , wherein the depth of the FIFO structure comprises:

a hardware depth, comprising a depth of the first portion of the FIFO structure;

a memory depth, comprising a depth of the second portion of the FIFO structure; and

wherein the depth comprises the sum of the hardware depth and the memory depth.

32. The system of claim 29 ,

wherein the FIFO structure comprises a front, from which data may be read, and a rear, to which data may be written; and

wherein, if the direction of the FIFO structure is configured to be memory to programmable hardware element, the first portion of the FIFO structure includes the front of the FIFO structure and the second portion of the FIFO structure includes the rear of the FIFO structure, and if the direction of the FIFO structure is configured to be programmable hardware element to memory, the first portion of the FIFO structure includes the rear of the FIFO structure and the second portion of the FIFO structure includes the front of the FIFO structure.

33. The system of claim 29 , wherein the second node is configurable to specify a desired function of the FIFO structure, wherein the desired function of the FIFO structure comprises one or more of:

read operations;

write operations;

start operations;

stop operations; and

configure operations.

34. The system of claim 33 , further comprising:

a computer system, comprising:

a processor; and

memory, coupled to the processor, wherein the memory stores program instructions;

wherein, to specify a desired function of the FIFO structure, the program instructions are executable by the processor to:

provide one or more selectable options for specifying the desired function of the FIFO structure; and

receive input selecting one of the one or more selectable options to specify the desired function of the FIFO structure;

wherein, after said selecting, the second node is executable to invoke the desired function of the FIFO structure.

35. The system of claim 34 , further comprising:

the controller, comprising:

a processor; and

the memory, coupled to the processor; and

the programmable hardware element, coupled to the controller.

36. The system of claim 35 , wherein the FIFO structure is a Direct Access Memory (DMA) FIFO, the system further comprising:

a DMA controller comprised on or coupled to the programmable hardware element, wherein the DMA controller is operable to receive instructions from the first node and the second node and directly transfer data between the programmable hardware element and the memory of the controller system in accordance with the received instructions.

37. The system of claim 36 , wherein the DMA controller comprises:

first DMA logic, coupled to or comprised on the programmable hardware element, wherein the first DMA logic implements DMA functionality; and

second DMA logic, comprised on the programmable hardware element, wherein the second DMA logic implements structure functionality for the first DMA logic.

38. The system of claim 37 , wherein the program instructions stored in the memory of the computer system are further executable by the processor of the computer system to:

automatically generate the second DMA logic in response to inclusion of the first node in the first graphical program and in accordance with configuration information for the DMA structure, wherein the second DMA logic is deployable with the first graphical program to the programmable hardware element.

39. The system of claim 38 , wherein the program instructions stored in the memory of the computer system are further executable by the processor of the computer system to:

deploy the first graphical program and the second DMA logic onto the programmable hardware element; and

deploy the second graphical program to the controller.

40. The system of claim 39 ,

wherein the programmable hardware element is operable to execute the first graphical program and the second DMA logic; and

wherein the controller is operable to execute the second graphical program concurrently with execution of the first graphical program on the programmable hardware element to cooperatively perform the specified task.

41. The system of claim 35 , wherein the computer system comprises the controller.

42. The system of claim 29 , wherein data are transferred between the first and second graphical programs via program instructions executed by the processor of the computer system.

43. The method of claim 42 , wherein the data are transferred between the first and second graphical programs via program instructions executed by the processor of the computer system using one or more of:

programmed I/O; or

interrupt-driven I/O.