Bit field operation circuit
View Patent ↗A bit field operation circuit has a first shift unit, a mask shift amount control circuit, a second shift unit, a logic operation unit, and a selection unit. The first shift unit outputs a first intermediate data based on a first control signal. The mask shift amount control circuit outputs a mask shift control signal in accordance with a mask shift amount. The second shift unit outputs a second intermediate data based on a mask shift control signal. The third shift unit outputs a third intermediate data based on the first control signal. The logic operation unit performs logical operation of the second intermediate data and the third intermediate data, and outputs a mask selection data. The selection unit selects either one of the first intermediate data or the second input data based on the mask selection data to output as output data.
1. A bit field operation circuit comprising:
a first shift unit that shifts n bits (n being an integer of 2 or more) of first input data in a direction from a least significant bit to a most significant bit based on a first control signal, and generates and outputs n bits of first intermediate data;
a mask shift amount control circuit to which the first control signal, a second control signal and a third control signal are input, that determines a mask shift amount on the basis of the first, second and third control signals, and outputs a mask shift control signal in accordance with the mask shift amount;
a second shift unit that shifts n bits of reference data in a direction from the most significant bit to the least significant bit based on the mask shift control signal, and generates and outputs n bits of second intermediate data;
a third shift unit that shifts the reference data in a direction from the least significant bit to the most significant bit on the basis of the first control signal, and generates and outputs n bits of third intermediate data;
a logic operation unit that performs a logical operation on the second intermediate data and the third intermediate data, and generates and outputs n bits of mask selection data; and
a selection unit that selects either one of the first intermediate data or n bits of second input data based on the mask selection data so as to output as n bits of output data.
2. The bit field operation circuit of claim 1 , wherein the logic operation unit performs the logical operation on the second intermediate data and the third intermediate data on a per bit basis, and outputs the mask selection data.
3. The bit field operation circuit of claim 1 , wherein the logic operation unit performs a negative OR operation on the second intermediate data and the third intermediate data on a per bit basis, and outputs the mask selection data.
4. The bit field operation circuit of claim 1 , wherein the mask shift amount control circuit comprises:
an adder that adds the first control signal and the second control signal so as to output a fourth control signal; and
a subtracter that subtracts the fourth control signal from the third control signal so as to output the mask shift control signal.