Method and system for reducing instruction storage space for a processor integrated in a network adapter chip
View Patent ↗Certain embodiments for reducing instruction storage space for a processor integrated in a network adapter chip may include generating MIPS instructions from corresponding new instructions. The new instructions may be in patch code instruction (PCI) format. The new instructions may be decoded and the MIPS instructions may be generated by a MIPS processor within a network adapter chip. Decoding the new instructions may also be referred to as interpreting the new instructions. The new instructions may comprise fewer bits than the generated MIPS instructions. The generated MIPS instructions may be executed by the MIPS processor within the network adapter chip.
1. A method for reducing storage space for instructions, the method comprising:
storing new instructions in a nonvolatile random access memory;
generating, within a network adapter chip, native processor machine language instructions from corresponding new instructions stored in the nonvolatile random access memory that is external to the network adapter chip, the new instructions comprising fewer bits than said native processor machine language instructions, the native processor machine language instructions being configured in a native processor machine language instruction format, the new instructions being configured into a patch code instruction format in which the new instructions do not comprise a native processor machine language, the patch code instruction format comprising a memory map format for use with the nonvolatile random access memory, the memory map format comprising a signature field, a format field, a flag field and a data block, the flag field comprising a first flag, a second flag and other flags, the first flag indicating that a service code patch is present in the data block, the second flag indicating that an initialization code patch is present in the data block, one or more of the other flags relating to power supplied to the network adapter chip, the new instructions being configured into the patch code instruction format to save memory space in the nonvolatile random access memory and being configured to modify boot functionality of a self boot code, said network adapter chip comprising a physical layer, a media access controller layer, a processor, a random access memory and a read only memory, the physical layer being connected to a gigabit Ethernet and handling voice and data traffic, the native processor machine language instructions resulting from decoding of the new instructions by the processor, the new instructions that are not able to be decoded by the processor being ignored without causing an interrupt or an exception, the read only memory providing the self boot code that generates said native processor machine language instructions from the corresponding new instructions stored in the nonvolatile memory during a boot phase of the network adapter chip, the read only memory providing the self boot code that generates said native processor machine language instructions from the corresponding new instructions stored in the nonvolatile memory that execute in a loop after the boot phase of the network adapter chip; and
executing said generated native processor machine language instructions within said network adapter chip.
2. The method according to claim 1 , comprising interpreting within said network adapter chip, said corresponding new instructions.
3. The method according to claim 1 , wherein said generation occurs during bootup of said network adapter chip.
4. The method according to claim 1 , wherein said new instructions are stored in memory external to said network adapter chip.
5. The method according to claim 4 , comprising during bootup of said network adapter chip, copying said new instructions from said memory external to said network adapter chip to on-chip memory within said network adapter chip.
6. The method according to claim 5 , comprising validating data stored in at least a portion of said memory external to said network adapter chip.
7. The method according to claim 6 , comprising determining a format of said data stored in said memory external to said network adapter chip.
8. The method according to claim 1 , wherein execution of said generated native processor machine language instructions from said corresponding new instructions occurs during runtime.
9. The method according to claim 1 , comprising executing within said network adapter chip, code patch comprising said generated native processor machine language instructions.
10. The method according to claim 9 , wherein said code patch comprises instruction code patch and service code patch.
11. A machine-readable storage having stored thereon, a computer program having at least one code section for reducing storage space for instructions, the at least one code section being executable by a machine for causing the machine to perform steps comprising:
generating, within a network adapter chip, native processor machine language instructions from corresponding new instructions stored in a nonvolatile memory during a boot phase of the network adapter chip, the new instructions comprising fewer bits than said native processor machine language instructions, the native processor machine language instructions being configured in a native processor machine language instruction format, the new instructions being configured into a patch code instruction format in which the new instructions do not comprise a native processor machine language, the patch code instruction format comprising a memory map format for use with the nonvolatile random access memory, the memory map format comprising a signature field, a format field, a flag field and a data block, the flag field comprising a first flag, a second flag and other flags, the first flag indicating that a service code patch is present in the data block, the second flag indicating that an initialization code patch is present in the data block, one or more of the other flags relating to power supplied to the network adapter chip, the new instructions being configured into the patch code instruction format to save memory space in the nonvolatile memory and being configured to modify boot functionality of a self boot code, the native processor machine language instructions resulting from decoding of the new instructions by the processor, the new instructions that are not able to be decoded by the processor being ignored without causing an interrupt or an exception; and
executing said generated native processor machine language instructions within said network adapter chip.
12. The machine-readable storage according to claim 11 , comprising code for interpreting within said network adapter chip, said corresponding new instructions.
13. The machine-readable storage according to claim 11 , wherein said generation occurs during bootup of said network adapter chip.
14. The machine-readable storage according to claim 11 , wherein said new instructions are stored in memory external to said network adapter chip.
15. The machine-readable storage according to claim 14 , comprising code for copying said new instructions from said memory external to said network adapter chip to on-chip memory within said network adapter chip during bootup of said network adapter chip.
16. The machine-readable storage according to claim 15 , comprising code for validating data stored in at least a portion of said memory external to said network adapter chip.
17. The machine-readable storage according to claim 16 , comprising code for determining a format of said data stored in said memory external to said network adapter chip.
18. The machine-readable storage according to claim 11 , wherein execution of said generated native processor machine language instructions from said corresponding new instructions occurs during runtime.
19. The machine-readable storage according to claim 11 , comprising code for executing within said network adapter chip, code patch comprising said generated native processor machine language instructions.
20. The machine-readable storage according to claim 19 , wherein said code patch comprises instruction code patch and service code patch.
21. A system for reducing storage space for instructions, the system comprising:
a nonvolatile memory coupled to a processor of a network adapter chip, the nonvolatile memory being external to the network adapter chip;
the processor configured to generate, within the network adapter chip, native processor machine language instructions from corresponding new instructions in nonvolatile memory during a boot phase of the network adapter chip, the new instructions comprising fewer bits than said native processor machine language instructions, the native processor machine language instructions being configured in a native processor machine language instruction format, the new instructions being configured into a patch code instruction format in which the new instructions do not comprise a native processor machine language, the patch code instruction format comprising a memory map format for use with the nonvolatile random access memory, the memory map format comprising a signature field, a format field, a flag field and a data block, the flag field comprising a first flag, a second flag and other flags, the first flag indicating that a service code patch is present in the data block, the second flag indicating that an initialization code patch is present in the data block, one or more of the other flags relating to power supplied to the network adapter chip, the new instructions being configured into the patch code instruction format to save memory space in the nonvolatile memory and being configured to modify boot functionality of a self boot code, said network adapter chip comprising a physical layer, a media access controller layer, a processor, a random access memory and a read only memory, the physical layer being connected to a network and handling voice and data traffic, the native processor machine language instructions resulting from decoding of the new instructions by the processor, the new instructions that are not able to be decoded by the processor being ignored without causing an interrupt or an exception, the read only memory providing the self boot code that generates said native processor machine language instructions from the corresponding new instructions stored in the nonvolatile memory during a boot phase of the network adapter chip; and
said processor executes said generated native processor machine language instructions within said network adapter chip.
22. The system according to claim 21 , comprising said processor that interprets within said network adapter chip, said corresponding new instructions.
23. The system according to claim 21 , wherein said generation occurs during bootup of said network adapter chip.
24. The system according to claim 21 , wherein said new instructions are stored in memory external to said network adapter chip.
25. The system according to claim 24 , comprising said processor that copies said new instructions from said memory external to said network adapter chip to on-chip memory within said network adapter chip during bootup of said network adapter chip.
26. The system according to claim 25 , comprising said processor that validates data stored in at least a portion of said memory external to said network adapter chip.
27. The system according to claim 26 , comprising said processor that determines a format of said data stored in said memory external to said network adapter chip.
28. The system according to claim 21 , wherein execution of said generated native processor machine language instructions from said corresponding new instructions occurs during runtime.
29. The system according to claim 21 , comprising said processor that executes within said network adapter chip, code patch comprising said generated native processor machine language instructions.
30. The system according to claim 29 , wherein said code patch comprises instruction code patch and service code patch.