Skew management in an interconnection system
View Patent ↗An interconnection system is described where data lanes may be exchanged between lines at intervals along a transmission path so that the differential time delay between bits on a plurality of the lines is reduced when determined at a receiving location. The data lanes may be bound to the lines through the operation of a configurable switch, or by a configurable switch in conjunction with predetermined manufactured connections, or a combination of the techniques. The wiring of a connectorized node module, which may include a memory device, may be configured so that the differential time delay between pairs of input lines of a node, as measured at the output of a node, is reduced.
1. A node, comprising:
a switch; and
an input port and an output port, each port having first, second, third and fourth lines, the input port receiving a data word on at least a pair of lines of the first, second third and fourth lines, data bits of the data word having a differential time delay therebetween,
wherein the switch is configurable to communicate between the input port and the output port so that the data bits of the data word received on the pair of lines of the input port are routed to a pair of lines of the output port and the pair of output lines is selected based on at least the differential time delay of the data bits of the data word;
the node further comprising:
a second output port, having first, second, third and fourth lines,
and to select between the first output port and the second output port so that the data bits of received on the pair of lines of the input port are routed to a pair of output lines of the second output port, the pair of output lines being selected based on at least the differential time delay of the received data word.
2. The node of claim 1 , further comprising a memory circuit, communicating with at least one of the input port or the output port.
3. A method for compensating for data skew in an interconnection system, the method comprising:
providing a node connectable to a signal bus, the node comprising at least a switch, a plurality of input lines and a plurality of output lines;
determining a first differential time delay of data bits of a data word received on a pair of input lines of the node; and
configuring the switch such that the data bits of the data word received on the pair of input lines of the node are routed to a pair of output lines of the node,
wherein the pair of output lines is selected based on the first differential time delay such that the data bits of the data word received at a second node are received with a second differential time delay that is different from the first differential time delay, when the second differential time delay is determined at the second node.
4. The method of claim 3 , wherein a line of the input lines of the node communicates with an output line of the output lines of the node, independent of the switch configuration.
5. The method of claim 3 wherein a word comprises two or more bits.
6. The method of claim 3 , wherein the switch is configured prior to receipt of the data word.
7. A method for compensating for data skew in an interconnection system, the method comprising:
providing a node connectable to a signal bus, the node comprising at least a switch, a plurality of input lines and a plurality of output lines;
determining a first differential time delay of data bits of a data word received on a pair of input lines of the node;
configuring the switch such that the data bits of the data word received on the pair of input lines of the node are routed to a pair of output lines of the node; and
determining the first differential time delay prior to receipt of the data word,
wherein the pair of output lines is selected based on the first differential time delay.
8. A method for compensating for data skew in an interconnection system, the method comprising:
providing a node connectable to a signal bus, the node comprising at least a switch, a first output port and a second output port, a plurality of input lines and a plurality of output lines;
determining a first differential time delay of data bits of a data word received on a pair of input lines of the node; and
configuring the switch such that the data bits of the data word received on the pair of input lines of the node are routed to a pair of output lines of the node,
wherein the pair of output lines is selected based on the first differential time delay and the pair of output lines of the first output port or second output port selected depends on the output port of the first and second output ports that is selected.
9. A node, comprising:
a switch; and
an input port and an output port each port having first, second, third and fourth lines, the input port receiving a data word on at least a pair of lines of the first, second third and fourth lines, data bits of the data word having a differential time delay therebetween,
wherein the switch is configurable to communicate between the input port and the output port so that the data bits of the data word received on the pair of lines of the input port are routed to a pair of lines of the output port and the pair of output lines is selected based on at least the differential time delay of the data bits of the data word; and, the differential time delay is determined at output terminals of the node.
10. A node, comprising:
a switch; and
an input port and an output port, each port having first, second, third and fourth lines, the input port receiving a data word on at least a pair of lines of the first, second third and fourth lines, data bits of the data word having a differential time delay therebetween,
wherein the switch is configurable to communicate between the input port and the output port so that the data bits of the data word received on the pair of lines of the input port are routed to a pair of lines of the output port and the pair of output lines is selected based on at least the differential time delay of the data bits of the data word; and, the differential delay is determined at an input to the switch.