Performance monitoring device and method thereof
View Patent ↗A performance monitoring device and method are disclosed. The device monitors performance events of a processor. A counter is adjusted in response to the occurrence of a particular performance event. The counter can be associated with a particular instruction address range, or a data address range, so that the counter is adjusted only when the performance event occurs at the instruction address range or the data address range. Accordingly, the information stored in the counter can be analyzed to determine if a particular instruction address range or data address range results in a particular performance event. Multiple counters, each associated with a different performance event, instruction address range, or data address range, can be employed to allow for a detailed analysis of which portions of a program lead to particular performance events.
1. A method, comprising:
receiving a first performance event indicator associated with a first instruction;
receiving a first data address associated with the first performance event indicator; and
adjusting a first counter based on the first performance event indicator, based on a relationship between the first data address and a first criterion, and based on a relationship between a first instruction address associated with the first instruction and a second criterion.
2. The method of claim 1 , wherein the first criterion comprises a first address range and the second criterion comprises a second address range and adjusting the first counter comprises adjusting the first counter in response to the first instruction address being within the first address range and the first data address being within the second address range.
3. The method of claim 1 , wherein the first criterion comprises a first address range and a second address range and the second criterion comprises a third address range and wherein adjusting the first counter comprises adjusting the first counter in response to the first instruction address being within the first address range or the second address range and the first data address being within the third address range.
4. The method of claim 1 , wherein the first criterion comprises a first address range and the second criterion comprises a second address range and a third address range and wherein adjusting the first counter comprises adjusting the first counter in response to the first instruction address being within the first address range and the first data address being within the second address range or the third address range.
5. The method of claim 1 , wherein the first criterion comprises a first address range and a second address range and the second criterion comprises a third address range and a fourth address range and wherein adjusting the first counter comprises adjusting the first counter in response to the instruction address being within the first address range or the second address range and the data address being within the third address range or the fourth address range.
6. The method of claim 1 , further comprising:
receiving a second performance event indicator associated with a second instruction; and
adjusting a second counter based on the second performance event indicator, a relationship between a second instruction address associated with the second instruction and a third criterion, and the relationship between a second data address associated with the second instruction and a fourth criterion.
7. The method of claim 6 , wherein the first criterion comprises a first address range, the second criterion comprises a second address range, the third criterion comprises a third address range, and the fourth criterion comprises a fourth address range, and wherein adjusting the first counter comprises adjusting the first counter in response to the first instruction address being within the first address range and the first data address being within the second address range; and wherein adjusting the second counter comprises adjusting the second counter in response to the second instruction address being within the third address range and the first data address being within the fourth address range.
8. The method of claim 6 , wherein the first criterion comprises a first address range, the second criterion comprises a second address range, the third criterion comprises the first address range, and the fourth criterion comprises a third address range, and wherein adjusting the first counter comprises adjusting the first counter in response to the first instruction address being within the first address range and the first data address being within the second address range, and wherein adjusting the second counter comprises adjusting the first counter in response to the second instruction address being within the first address range and the first data address being within the third address range.
9. The method of claim 6 , wherein the first criterion comprises a first address range, the second criterion comprises a second address range, the third criterion comprises a third address range, and the fourth criterion comprises the second address range, and adjusting the first counter comprises adjusting the first counter in response to the first instruction address being within a first address range and the first data address being within a second address range; and
wherein adjusting the second counter comprises adjusting the first counter in response to the second instruction address being within a third address range and the first data address being within the second address range.
10. The method of claim 1 , further comprising generating an interrupt signal based on a relationship between a value stored in the first counter and a threshold.
11. The method of claim 1 , wherein the first performance event indicator is representative of an instruction processing performance event.
12. The method of claim 1 , wherein the first performance event indicator is representative of a branch related performance event.
13. A device, comprising:
a processor;
a first register configured to store a first address range;
a second register configured to store a second address range;
a control module comprising;
a first input configured to receive an indicator of a first performance event of the processor, the performance event associated with an execution of first instruction by the processor; and
a first output configured to provide a first adjustment indicator signal based on the indicator of the first performance event, an instruction address associated with the first instruction, a data address associated with the instruction, the first address range, and the second address range; and
a first counter comprising an input coupled to the first output of the control module, the first counter configured to adjust a stored value based on the first adjustment indicator signal being in a first select state.
14. The device of claim 13 , wherein the control module is configured to place the first adjustment indicator signal in the first select state in response to the instruction address being within the first address range and the data address being within the second address range.
15. The device of claim 13 , wherein the control module is configured to place the first adjustment indicator signal in the select state in response to the instruction address being outside of the first address range and the data address being within the second address range.
16. The device of claim 13 , further comprising:
a third register configured to store a third address range;
a fourth register configured to store a fourth address range; and
wherein the control module further comprises a fourth input coupled to the output of the third register and a fifth input coupled to the output of the fourth register.
17. The device of claim 16 , wherein the control module is configured to place the first adjustment indicator signal in the select state in response to the instruction address being within the first address range or the second address range and the data address being within the third address range.
18. The device of claim 16 , wherein the control module is configured to place the first adjustment indicator signal in the select state in response to the first instruction address being within the first address range and the first data address being within the second address range or the third address range.
19. The device of claim 16 , wherein the control module comprises a second output configured to provide a second adjustment indicator based on an indicator of a second performance event, an instruction address associated with a second instruction, a data address associated with the second instruction, the third address range, and the fourth address range and further comprising:
a second counter comprising an input coupled to the second output of the control module, the second counter configured to adjust a stored value based on the second adjustment indicator signal being in a second select state.
20. The device of claim 19 , wherein the control module is configured to place the first adjustment indicator signal in the first state in response to the first instruction address being within the first address range and the first data address being within the second address range;
and is configured to place the second adjustment indicator in the second state in response to the second instruction address being within the third address range and the second data address being within the fourth address range.