Organic light emitting diode display and method for manufacturing the same
View Patent ↗An improved OLED display includes a substrate, a semiconductor having a uniform thickness formed on the substrate, first and second ohmic contacts, and a driving voltage line having an input electrode and an output electrode. An insulating layer is formed on the driving voltage line and the output electrode. A control electrode is formed on the insulating layer and overlaps the semiconductor. The method of manufacturing the OLED display entails forming a semiconductor on a substrate, forming a photoresist film on the semiconductor, forming a doped amorphous silicon layer on the photoresist film, removing the photoresist film along with a portion of the doped amorphous silicon disposed on the photoresist film to form first and second ohmic contacts, respectively forming input and output electrodes on the first and second ohmic contacts, forming an insulating layer on the input and output electrodes, and forming a control electrode on the insulating layer.
1. A method for manufacturing an organic light emitting diode display, comprising:
forming a first semiconductor on a substrate;
forming a photoresist film on the first semiconductor;
forming a doped amorphous silicon layer on the photoresist film;
removing the photoresist film along the portion of the doped amorphous silicon disposed on the photoresist film to form first and second ohmic contacts;
respectively forming first input and first output electrodes on the first and second ohmic contacts;
forming a first insulating layer on the first input and first output electrodes; and
forming a first control electrode on the first insulating layer.
2. The method of claim 1 , further comprising:
forming a second semiconductor on the substrate;
forming third and fourth ohmic contacts on the second semiconductor;
forming a second input electrode on the third ohmic contact;
forming a second output electrode electrically connected to the first input electrode on the fourth ohmic contact; and
forming a second control electrode overlapping the second semiconductor on the first insulating layer.
3. The method of claim 1 , further comprising:
forming a second control electrode on the first insulating layer;
forming a second insulating layer on the second control electrode;
forming a second semiconductor overlapping the second control electrode on the second insulating layer;
forming third and fourth ohmic contacts on the second semiconductor; and
respectively forming a second output electrode electrically connected to the first control electrode, and a second input electrode, on the third and fourth ohmic contacts.
4. The method of claim 1 , further comprising:
forming a second control electrode on the substrate;
forming a second semiconductor overlapping the second control electrode on the first insulating layer;
forming third and fourth ohmic contacts on the second semiconductor; and
respectively forming a second output electrode electrically connected to the first control electrode, and a second input electrode, on the third and fourth ohmic contacts.
5. The method of claim 1 , wherein the amorphous silicon layer is deposited at a temperature less than 150 degrees.
6. The method of claim 1 , wherein the substrate is thermal-treated at a temperature of about 450 degree after forming the first and second ohmic contacts.
7. The method of claim 1 , further comprising:
HF cleaning the substrate after thermal-treating the substrate; and
plasma treating the substrate to stabilize the first and second semiconductors.
8. The method of claim 7 wherein the plasma treatment is performed under the conditions of about 200 Watt/12,000 mm 2 power and about 1000-3000 mT pressure with a flow rate of about 1000-3000 sccm for 90-180 seconds.
9. The method of claim 7 , wherein the amorphous silicon layer is crystallized by solid phase crystallization (SPC) and is patterned to form the first and second semiconductors.
10. The method of claim 1 , wherein the photoresist film has openings extending to the portions of the first semiconductor, and the openings have substantially the same shapes as the first and second ohmic contacts in plan view.