Semiconductor device and manufacturing method thereof
View Patent ↗A semiconductor device and a method of manufacturing a semiconductor device. A semiconductor device may include an epitaxial layer over a semiconductor substrate, a first well region over a epitaxial layer, a first isolation layer and/or a third isolation layer at opposite sides of said first well region and/or a second isolation layer over a first well region between first and third isolation layers. A semiconductor device may include a gate over a second isolation layer. A semiconductor device may include a second well region over a first well region between a third isolation layer and a gate, a first ion-implanted region over a second well region between a third isolation layer and a gate, and/or a second ion-implanted region between a first ion-implanted region and a gate. A semiconductor device may include an accumulation channel between a second well region and a gate.
1. A method comprising:
forming an epitaxial layer over a semiconductor substrate;
forming a first well region within said epitaxial layer;
forming a first isolation layer and a third isolation layer at opposite sides of said first well region;
forming a second isolation layer within said first well region between said first and third isolation layers;
forming a second well region within said first well region between said third isolation layer and said second isolation layer;
forming a first ion-implanted region within said second well region;
forming a second ion-implanted region between said first ion-implanted region and said second isolation layer;
forming a third ion-implanted region between said second isolation layer and said first isolation layer;
diffusing said second well region including said first and second ion-implanted regions using a thermal treatment; and
forming an accumulation channel between said diffused second well region and a region where a gate is to be formed, wherein said accumulation channel is formed in a process comprising at least one of a lower implant dose and a lower ion implantation energy than for said second ion-implanted region.
2. The method of claim 1 , comprising a laterally diffused metal oxide semiconductor device.
3. The method of claim 1 , wherein said epitaxial layer comprises a first conductivity type.
4. The method of claim 1 , wherein said first well region comprises a second conductivity type.
5. The method of claim 1 , wherein said second well region is formed over said first well region adjacent to said third isolation layer.
6. The method of claim 1 , wherein said second well region comprises a first conductivity and functions as a body of said first conductivity.
7. The method of claim 1 , wherein at least one of said first ion-implanted region, second ion-implanted region and third ion-implanted region are formed in a process comprising at least one of a lower implant dose and a lower ion implantation energy than for said second well region.
8. The method of claim 1 , wherein said first ion-implanted region comprises a first conductivity type.
9. The method of claim 1 , wherein said second ion-implanted region and said third ion-implanted region comprise a second conductivity type.
10. The method of claim 1 , wherein said accumulation channel is formed comprising a shallower depth than said second ion-implanted region.
11. The method of claim 1 , comprising:
forming a gate dielectric over said accumulation channel, said first well region between said second isolation layer and said accumulation channel, and said second isolation layer; and
forming a gate electrode over said gate dielectric.