Method of manufacturing a semiconductor device
View Patent ↗Provided is a manufacturing method of a semiconductor device, which comprises forming a film stack of a gate insulating film, a charge storage film, insulating film, polysilicon film, silicon oxide film, silicon nitride film and cap insulating film over a semiconductor substrate; removing the film stack by photolithography and etching from a low breakdown voltage MISFET formation region and a high breakdown voltage MISFET formation region; forming gate insulating films, polysilicon film and cap insulating film over the semiconductor substrate, forming a gate electrode in the low breakdown voltage MISFET formation region and high breakdown voltage MISFET formation region, and then forming a gate electrode in a memory cell formation region. By the manufacturing technology of a semiconductor device for forming the gate electrodes of a first MISFET and a second MISFET in different steps, the present invention makes it possible to provide the first MISFET and the second MISFET each having improved reliability.
1. A manufacturing method of a semiconductor device for forming a first MISFET over a first region of a semiconductor substrate and a second MISFET over a second region of the semiconductor substrate, which comprises the steps of:
(a) forming a first insulating film over the first region and the second region;
(b) forming a first metal film over the first insulating film;
(c) removing the first metal film and the first insulating film formed over the second region;
(d) after the step (c), forming a second insulating film over the second region and the first metal film over the first region;
(e) forming a second metal film over the second insulating film, wherein a second material composing the second metal film is different from a first material composing the first metal film;
(f) patterning the second metal film and the second insulating film formed over the second region to form a second gate electrode and a second gate insulating film of the second MISFET; and
(g) after the step (f), patterning the first metal film and the first insulating film formed over the first region to form a first gate electrode and a first gate insulating film of the first MISFET.
2. A manufacturing method of a semiconductor device according to claim 1 ,
wherein the first MISFET is an n-channel MISFET,
wherein the second MISFET is a p-channel MISFET,
wherein the first metal has a work function close to the conduction band of silicon, and
wherein the second metal has a work function close to the valence band of silicon.
3. A manufacturing method of a semiconductor device according to claim 2 ,
wherein the first metal film is formed of a tantalum film.
4. A manufacturing method of a semiconductor device according to claim 2 ,
wherein the second metal film is formed of a platinum film.
5. A manufacturing method of a semiconductor device according to claim 1 ,
wherein the first MISFET is a p-channel MISFET,
wherein the second MISFET is an n-channel MISFET,
wherein the first metal has a work function close to the valence band of silicon, and
wherein the second metal has a work function close to the conduction band of silicon.
6. A manufacturing method of a semiconductor device according to claim 5 ,
wherein the second metal film is formed of a tantalum film.
7. A manufacturing method of a semiconductor device according to claim 5 ,
wherein the first metal film is formed of a platinum film.
8. A manufacturing method of a semiconductor device according to claim 1 ,
wherein in the step (f), the second metal film and the second insulating film formed over the first metal film are removed.
9. A manufacturing method of a semiconductor device according to claim 1 ,
wherein the step (f) includes keeping selectively the second metal film and the second insulating film formed over the first metal film, and
wherein in the step (g), the first metal film and the first insulating film are patterned by using the second metal film and the second insulating film formed selectively over the first metal film as a hard mask.
10. A manufacturing method of a semiconductor device according to claim 1 ,
wherein a dummy pattern has been formed in a boundary region between the first region and the second region.
11. A manufacturing method of a semiconductor device for forming a first MISFET over a first region of a semiconductor substrate and a second MISFET over a second region of the semiconductor substrate, which comprises the steps of:
(a) forming a first insulating film over the first region and the second region, wherein the first insulating film includes a hafnium oxide film;
(b) forming a first metal film over the first insulating film;
(c) removing the first metal film and the first insulating film formed over the second region;
(d) after the step (c), forming a second insulating film over the second region and over the first metal film of the first region, wherein the second insulating film includes a hafnium oxide film;
(e) forming a second metal film over the second insulating film, wherein a second material composing the second metal film is different from a first material composing the first metal film;
(f) patterning the second metal film and the second insulating film formed over the second region to form a second gate electrode and a second gate insulating film of the second MISFET; and
(g) after the step (f), patterning the first metal film and the first insulating film formed over the first region to form a first gate electrode and a first gate insulating film of the first MISFET.
12. A manufacturing method of a semiconductor device according to claim 11 ,
wherein the first MISFET is an n-channel MISFET,
wherein the second MISFET is a p-channel MISFET,
wherein the first metal has a work function close to the conduction band of silicon, and
wherein the second metal has a work function close to the valence band of silicon.
13. A manufacturing method of a semiconductor device according to claim 12 ,
wherein the first metal film is formed of a tantalum film.
14. A manufacturing method of a semiconductor device according to claim 12 ,
wherein the second metal film is formed of a platinum film.
15. A manufacturing method of a semiconductor device according to claim 11 ,
wherein the first MISFET is a p-channel MISFET,
wherein the second MISFET is an n-channel MISFET,
wherein the first metal has a work function close to the valence band of silicon, and
wherein the second metal has a work function close to the conduction band of silicon.
16. A manufacturing method of a semiconductor device according to claim 15 ,
wherein the second metal film is formed of a tantalum film.
17. A manufacturing method of a semiconductor device according to claim 15 ,
wherein the first metal film is formed of a platinum film.
18. A manufacturing method of a semiconductor device according to claim 11 ,
wherein in the step (f), the second metal film and the second insulating film formed over the first metal film are removed.
19. A manufacturing method of a semiconductor device according to claim 11 ,
wherein the step (f) includes keeping selectively the second metal film and the second insulating film formed over the first metal film, and
wherein in the step (g), the first metal film and the first insulating film are patterned by using the second metal film and the second insulating film formed selectively over the first metal film as a hard mask.
20. A manufacturing method of a semiconductor device according to claim 11 ,
wherein a dummy pattern has been formed in a boundary region between the first region and the second region.
21. A manufacturing method of a semiconductor device according to claim 11 ,
wherein the first and second insulating films are each selected from the group consisting a HfAlON film, a HfON film, a HfSiO film, a HfSiON film, a HfAlO film, and a hafnium insulating film having introduced tantalum oxide, niobium oxide, titanium oxide, zirconium oxide, lanthanum oxide or yttrium oxide.