Lateral insulated gate bipolar transistor having a retrograde doping profile in base region and method of manufacture thereof
View Patent ↗In a semiconductor device of the present invention, a first base region 16 is extended to a part under a gate electrode 7 while having a vertical concentration profile of an impurity that increases from the surface of a semiconductor layer 3 and becomes maximum under an emitter region 5 , and the length in the lateral direction from a point where the impurity concentration becomes maximum located under an end of the gate electrode 7 to the boundary with a second base region 15 is not smaller than the length in the vertical direction from the point where the impurity concentration becomes maximum to the boundary with the second base region 15.
1. A method of manufacturing a semiconductor device, comprising:
forming a first base region of a second conductivity type on a surface of a semiconductor layer;
forming below said first base region a second base region having a lower concentration and a larger depth of an impurity of the second conductivity type than said first base region;
forming a buffer region of the second conductivity type in said semiconductor layer apart from said second base region;
sequentially forming a gate insulating film and a gate electrode on said first base region;
forming an emitter region of a first conductivity type on a surface of said first base region; and
forming a collector region of the first conductivity type on a surface of said buffer layer
wherein the end portions of said first base region and said gate electrode overlap each other and
a length in a lateral direction from a point where an impurity concentration of the second conductivity type in said first base region becomes maximum under said emitter region and at an end of said gate electrode to a boundary between said first base region and said semiconductor layer is not smaller than a length in the vertical direction from said point to the underside of said first base region.
2. The method of claim 1 , wherein said first base region is formed before forming said gate insulating film using the implantation of boron ions with accelerating energy within a range between 150 KeV and 200 KeV, and a dose within a range between 3×10 13 and 1×10 14 ions/cm 2 .
3. The method of claim 1 , wherein said semiconductor layer is formed on a supporting substrate via an insulating layer.
4. The method of claim 1 , wherein said first base region is formed after forming said second base region.
5. The method of claim 1 , wherein said semiconductor layer is a substrate of the first conductivity type.
6. The method of claim 1 , wherein said semiconductor layer is a supporting substrate of the second conductivity type; said second base region is formed above a main surface of said supporting substrate; and said buffer region is formed in a well region of the first conductivity type, spaced internally apart from said first base region.
7. The method of claim 1 , wherein according to a plan view of said collector region, said collector region has a corner portion and a straight portion and is surrounded by said gate electrode, and said emitter region is located at the periphery of said collector region and is formed corresponding to said straight portion.