Charge trapping devices with field distribution layer over tunneling barrier

1. A memory cell comprising:

a semiconductor substrate having a surface with a source region and a drain region in the substrate and separated by a channel region;

a multilayer stack over the channel including a tunneling barrier dielectric structure with an effective oxide thickness of greater than 3 nanometers disposed on the surface of the substrate above the channel region, a conductive layer disposed above the tunneling barrier dielectric structure and above the channel region, a dielectric charge trapping structure disposed above the conductive layer and above the channel region, and a top dielectric structure disposed above the charge trapping structure and above the channel region; and

a word line disposed above the top dielectric structure and above the channel region; wherein the conductive layer in the multilayer stack has an area over the channel region equal within manufacturing limitations to an area of the channel re ion beneath the word line and between the source and drain.

2. The memory cell of claim 1 , wherein the channel region has a length between the source and the drain, and a width orthogonal to the length of less than 45 nanometers.

3. The memory cell of claim 1 , wherein the multilayer stack has an effective oxide thickness and the channel region has a length between the source and the drain, and a width orthogonal to the length less than 1.5 times the effective oxide thickness of the multilayer stack.

4. A memory cell comprising:

a semiconductor substrate having a surface with a source region and a drain region in the substrate and separated by a channel region;

a multilayer stack over the channel including a tunneling barrier dielectric structure with an effective oxide thickness of greater than 3 nanometers disposed on the surface of the substrate above the channel region, a conductive layer disposed above the tunneling barrier dielectric structure and above the channel region, a dielectric charge trapping structure disposed above the conductive layer and above the channel region, and a top dielectric structure disposed above the charge trapping structure and above the channel region; and

a top conductive layer disposed above the top dielectric structure and above the channel region, wherein the channel region has a length between the source and the drain, and a width orthogonal to the length, and the conductive layer in the multilayer stack has a width that is substantially equal to the width of the channel region and has a length that is substantially equal to the length of the channel region, and

wherein the conductive layer in the multilayer stack has a thickness less than 6 nanometers.

5. The memory cell of claim 1 , wherein the tunneling barrier dielectric structure comprises silicon dioxide.

6. The memory cell of claim 1 , wherein the tunneling barrier dielectric structure comprises silicon oxynitride.

7. The memory cell of claim 1 , wherein the tunneling barrier dielectric structure comprises a bandgap engineered tunneling barrier structure.

8. The memory cell of claim 7 , wherein the conductive layer comprises doped semiconductor material.

9. A memory cell comprising:

a semiconductor substrate having a surface with a source region and a drain region in the substrate and separated by a channel region;

a multilayer stack over the channel including a tunneling barrier dielectric structure with an effective oxide thickness of greater than 3 nanometers disposed on the surface of the substrate above the channel region, a conductive layer disposed above the tunneling barrier dielectric structure and above the channel region, a dielectric charge trapping structure disposed above the conductive layer and above the channel region, and a top dielectric structure disposed above the charge trapping structure and above the channel region; and

a top conductive layer disposed above the top dielectric structure and above the channel region, wherein the conductive layer in the multilayer stack has a thickness less than 6 nanometers.

10. The memory cell of claim 1 , wherein the conductive layer comprises metal.

11. The memory cell of claim 1 , wherein the charge trapping structure comprises silicon nitride.

12. The memory cell of claim 1 , wherein the charge trapping structure comprises a silicon dioxide layer and a silicon nitride layer disposed above the silicon dioxide layer.

13. A memory device comprising:

an array of memory cells on a semiconductor substrate arranged in a plurality of NAND strings;

the memory cells in the respective NAND strings being coupled in series, and comprising a source region and a drain region in the substrate and separated by a channel region, a tunneling barrier dielectric structure with an effective oxide thickness of greater than 3 nanometers disposed above the channel region, a conductive layer disposed above the tunneling barrier dielectric structure and above the channel region, a dielectric charge trapping structure disposed above the conductive layer and above the channel region, a top dielectric structure disposed above the charge trapping structure, and a top conductive layer disposed above the top dielectric structure and above the channel region;

a row decoder;

a column decoder;

sense amplifiers;

at least one input port;

at least one output port;

data-in structures; and

bias arrangement state machine.