Delay stabilization method and apparatus for video format conversion
View Patent ↗A method for stabilizing delay during conversion between Standard Definition (SD) video and High Definition (HD) video includes the step of establishing an integer divide ratio (M/N) corresponding to a ratio of clock rates with the output and input formats. The output clock rate is generated from the input clock rate by a Phase Lock Loop ( 104 ) using the M/N divide ratio to provide a known phase relationship between the two clocks rates at a repetitive interval. The video frame can be transferred at the known repetitive interval to provide coarse control over the input-to-output video delay. A separate fine tuning control (delay block) is provided to enable any programmable delay in video throughput to be accommodated to an accuracy of ±0.5 output pixel periods.
1. A method for stabilizing delay during format conversion of incoming video, the method comprising the steps:
decoding a frame start position from the incoming video;
transferring a frame start signal at a next upcoming predetermined (N) cycle interval of an input clock;
subtracting N input pixel periods of delay from a programmable video delay prior to application to the incoming video;
matching a scaler output to a nearest video line start position; and
applying a remainder, after division of the programmable delay by N, to provide fine delay control.
2. The method of claim 1 , further comprising converting the remainder to an output pixel period representation by multiplying by the factor N before said step of applying.
3. A method for stabilizing delay during conversion of incoming video from a first format to a second format, each having associated clock rates, the method comprising the steps:
establishing an integer divide ratio (M/N) corresponding to a ratio of clock rates associated with the second format and first formats;
generating an output clock rate from the first format clock rate using the integer divide ratio to provide a known phase relationship between the two clocks rates at a repetitive interval; and
transferring a video frame at the repetitive interval to provide control over video delay,
wherein said establishing and said generating steps further comprise:
decoding a frame start position from an input video stream;
transferring a frame start signal at a next upcoming predetermined (N) cycle interval of the first format clock rate;
subtracting N input pixel periods of delay prior to application of the incoming video; and
matching a scaler output to a nearest video line start position.
4. The method of claim 3 , further comprising:
applying a fine tuning output trim delay to the transferred video frame to provide fine control over the video delay.
5. The method of claim 4 , wherein said applying is performed on the transferred video frame at the output clock rate.
6. The method of claim 3 , further comprising determining a remainder, after division of a programmable delay (D) by a predetermined cycle interval (N), and applying the remainder to fine tune the video delay.
7. The method of claim 3 , further comprising aligning the transferred video frame video to one of the incoming video time base or a genlock time base derived from a received video reference signal.
8. The method of claim 3 , wherein said repetitive interval is less than both first and second format video line periods.
9. An apparatus for stabilizing delay during conversion of incoming video from a first format to a second format, each having associated clock rates, comprising:
a phase lock loop block for: (a) establishing an integer divide ratio (M/N) corresponding to a ratio of clock rates associated with the second format and first formats; and (b) generating the an output clock rate from the first format clock rate using the integer divide ratio to provide a known phase relationship between the two clock rates at a repetitive interval;
means for decoding a frame start position from the incoming video;
means for transferring a frame start signal at a next upcoming predetermined (N) cycle interval of the first format clock rate;
means for subtracting N input pixel periods of delay from a programmable video delay prior to application to the incoming video; and
means for matching a scaler output to a nearest video line start position generated from the phase lock loop block; and
means for transferring of a video frame timing signal at the repetitive interval to provide coarse control over an input-to-output video delay.
10. The apparatus of claim 9 , further comprising:
means for applying a fine tuning output trim delay to the transferred video frame to provide fine control over the input-to-output video delay.
11. The apparatus of claim 9 , further comprising:
means for determining a remainder, after division of the programmable delay (D) by the predetermined cycle interval (N); and
means for applying the remainder to a fine tuning output delay circuit.
12. The apparatus of claim 9 , further comprising means for aligning output video to one of an input video time base or a genlock time base derived from a received video reference signal.