Method of manufacturing semiconductor device
View Patent ↗A method for fabricating a semiconductor device to which a stress technique is applied and in which a leakage current caused by silicidation can be suppressed. The method includes forming an isolation region in a semiconductor substrate; forming a gate electrode over an element region defined by the isolation region formed in the semiconductor substrate; and forming a semiconductor lager in the element region at both sides of the gate electrode apart from at least part of the isolation region. By doing so, the formation of a spike near the isolation region is suppressed even if a silicide layer is formed. Accordingly, a leakage current caused by such a spike can be suppressed.
1. A method for fabricating a semiconductor device, the method comprising:
forming an isolation region in a semiconductor substrate;
forming a gate electrode over an element region defined by the isolation region formed in the semiconductor substrate;
forming semiconductor layers in the element region at both sides of the gate electrode apart from at least part of the isolation region;
forming an impurity region that is a source region or drain region between the isolation region and the semiconductor layers in the semiconductor substrate; and
forming silicide layers on the impurity region and the semiconductor layers.
2. The method according to claim 1 , wherein the semiconductor layers differ from the semiconductor substrate in lattice constant.
3. The method according to claim 1 , wherein:
the semiconductor substrate is a silicon substrate; and
the semiconductor layers are SiGe layers, SiGeC layers, or SiC layers.
4. The method according to claim 1 , wherein forming of the semiconductor layers includes:
forming a mask which covers at least part of portions of the element region contiguous to the isolation region;
forming recesses in the element region by using the mask; and
forming the semiconductor layers in the recesses.
5. The method according to claim 4 , wherein in the forming of the mask, the mask covers part of the element region so that the semiconductor layers are located apart from portions of the isolation region located in a direction of gate length of the gate electrode.
6. The method according to claim 4 , wherein in the forming of the mask, the mask covers part of the element region so that the semiconductor layers are located apart from portions of the isolation region located in a direction of gate width of the gate electrode.
7. The method according to claim 1 , wherein in the forming of the semiconductor layers, distances between the semiconductor layers and the isolation region are set to 5 nm to 100 nm.
8. The method according to claim 1 , wherein the forming of the silicide layers includes:
forming metal layers over the semiconductor layers; and
making the metal layers react with the semiconductor layers by heat treatment.
9. The method according to claim 1 , further comprising forming spacers on side walls of the gate electrode; wherein
the forming of the semiconductor layers includes forming a part of the semiconductor layers under the spacers.