Semiconductor device
View Patent ↗Provided is a method which is capable of producing polycrystalline silicon resistors with a high ratio accuracy so that a precision resistor circuit may be designed. A semiconductor device has a structure in which an occupation area of a metal portion covering a low concentration impurity region constituting each of the polycrystalline silicon resistors is adjusted so that ratio accuracy may be further corrected after a resistance is corrected.
1. A semiconductor device, comprising:
a semiconductor substrate;
a first insulating film on the semiconductor substrate;
a plurality of resistors having a same shape, which are disposed on the first insulating film and comprising polycrystalline silicon each having a low concentration impurity region and a high concentration impurity region abutting end portions of the low concentration impurity region;
a second insulating film overlying the plurality of resistors;
a contact hole extending through the second insulating film and exposing a portion of the high concentration impurity region;
a first metal portion comprising a metal wiring layer traversing the contact hole and connecting the plurality of resistors;
a second metal portion disposed on the second insulating film so as to cover the low concentration impurity region of a resistor group including one of a single resistor and more than two resistors connected to one another selected from the plurality of resistors; and
a third metal portion provided adjacent to the second metal portion and coupled to the second metal portion by a severable connection, such that the effective area of the second metal portion includes the third metal portion, wherein the third metal portion is subject to electrical separation from the second metal portion upon breaking the severable connection.
2. A semiconductor device according to claim 1 , wherein the severable connection between the second metal portion and the third metal portion comprises a fuse.
3. A semiconductor device according to claim 1 , wherein the severable connection between the second metal portion and the third metal portion comprises a metal connecting portion configured to be cut by laser.
4. A semiconductor device according to claim 1 , wherein the area of the second metal portion can be decreased by laser trimming.
5. A semiconductor device according to claim 1 , wherein the second metal portion is disposed so as to entirely cover the resistor group.
6. A semiconductor device according to claim 1 , wherein the second metal portion and the third metal portion comprises portions of the metal wiring layer.
7. A semiconductor device according to claim 1 , wherein a resistance ratio of the semiconductor device changes in direct proportion to the effective area of the second metal portion.