IP Library Granted Patent US 8,309,409
Granted Patent B2
US 8,309,409 · App. 13/027,761 · Granted Nov 13, 2012

Method for fabricating trench gate to prevent on voltage parasetic influences

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,309,409
App. No.
13/027,761
Granted
Nov 13, 2012
Kind
B2
Abstract

A semiconductor-device fabrication method includes forming a second semiconductor region of a second conductivity on a surface layer of a first semiconductor region of a first conductivity, the second semiconductor region having an impurity concentration higher than the first semiconductor region; forming a trench penetrating the second semiconductor region, to the first semiconductor region; embedding a first electrode inside the trench via an insulating film, at a height lower than a surface of the second semiconductor region; forming an interlayer insulating film inside the trench, covering the first electrode; leaving the interlayer insulating film on only a surface of the first electrode; removing the second semiconductor region such that the surface thereof is positioned lower than an interface between the first electrode and the interlayer insulating film; and forming a second electrode contacting the second semiconductor region and adjacent to the first electrode via the insulating film in the trench.

Claims (42)

1. A method of fabricating a semiconductor device comprising:

forming a second semiconductor region of a second conductivity type on a surface layer of a first semiconductor region of a first conductivity type, the second semiconductor region having an impurity concentration higher than that of the first semiconductor region;

forming a trench that penetrates the second semiconductor region to reach the first semiconductor region;

embedding a first electrode inside the trench via an insulating film, the first electrode not reaching the same height as a surface of the second semiconductor region;

forming an interlayer insulating film embedded inside the trench to cover the first electrode;

leaving the interlayer insulating film on only a surface of the first electrode;

removing the second semiconductor region such that the surface of the second semiconductor region is positioned lower than an interface between the first electrode and the interlayer insulating film; and

forming a second electrode that has a bottom surface that contacts the second semiconductor region and that has a side surface that contacts said insulating film, the second electrode being adjacent to the first electrode via the insulating film formed on a sidewall of the trench.

2. The method of fabricating a semiconductor device according to claim 1 , further comprising:

forming a third semiconductor region of the second conductivity type on a surface of the first semiconductor region, the third semiconductor region having an impurity concentration higher than that of the first semiconductor region; and

forming a third electrode on a surface of the third semiconductor region.

3. A method of fabricating a semiconductor device comprising:

forming a second semiconductor region of a second conductivity type on a surface layer of a first semiconductor region of a first conductivity type, the second semiconductor region having an impurity concentration higher than that of the first semiconductor region;

forming a trench that penetrates the second semiconductor region to reach the first semiconductor region;

embedding a first electrode inside the trench via an insulating film, the first electrode not reaching the same height as a surface of the second semiconductor region;

forming an interlayer insulating film embedded inside the trench to cover the first electrode;

leaving the interlayer insulating film on only a surface of the first electrode;

removing the second semiconductor region such that the surface of the second semiconductor region is positioned lower than an interface between the first electrode and the interlayer insulating film;

forming a second electrode that contacts the second semiconductor region, the second electrode being adjacent to the first electrode via the insulating film formed on a sidewall of the trench; and

wherein the second electrode is embedded in a recess portion made up of the second semiconductor region and the insulating film formed on the sidewall of the trench.

4. The method of fabricating a semiconductor device according to claim 3 , including forming said recess such as to be delineated by a substantially flat top surface of said second semiconductor region and the insulating film that forms a sidewall that is substantially perpendicular to said top surface of said second semiconductor region.

5. The method of fabricating a semiconductor device according to claim 4 , including forming said substantially flat top surface of said second semiconductor region such as to be substantially parallel to a front surface of a semiconductor substrate of said semiconductor device.

6. The method of fabricating a semiconductor device according to claim 4 , wherein said second electrode is in contact with said substantially flat top surface of said second semiconductor region and said sidewall of said insulating film, whereby forming a channel region in a region of the second semiconductor region adjacent to said first electrode via the insulating film enabling the semiconductor device to be fabricated without forming a source region on a surface layer of the second semiconductor region.

7. The method of fabricating a semiconductor device according to claim 4 , wherein two or more of said semiconductor devices are disposed on a single substrate.

8. A method of fabricating a semiconductor device comprising:

forming a second semiconductor region of a second conductivity type on a surface layer of a first semiconductor region of a first conductivity type, the second semiconductor region having an impurity concentration higher than that of the first semiconductor region;

forming a trench that penetrates the second semiconductor region to reach the first semiconductor region;

embedding a first electrode inside the trench via an insulating film, the first electrode not reaching the same height as a surface of the second semiconductor region;

forming an interlayer insulating film embedded inside the trench to cover the first electrode;

leaving the interlayer insulating film on only a surface of the first electrode;

removing the second semiconductor region such that the surface of the second semiconductor region is positioned lower than an interface between the first electrode and the interlayer insulating film;

forming a second electrode that contacts the second semiconductor region, the second electrode being adjacent to the first electrode via the insulating film formed on a sidewall of the trench; and

wherein the second semiconductor region is removed by etching using the interlayer insulating film as a mask.

9. A method of fabricating a semiconductor device comprising:

forming a second semiconductor region of a second conductivity type on a surface layer of a first semiconductor region of a first conductivity type, the second semiconductor region having an impurity concentration higher than that of the first semiconductor region;

forming a trench that penetrates the second semiconductor region to reach the first semiconductor region;

embedding a first electrode inside the trench via an insulating film, the first electrode not reaching the same height as a surface of the second semiconductor region;

forming an interlayer insulating film embedded inside the trench to cover the first electrode;

leaving the interlayer insulating film on only a surface of the first electrode;

removing the second semiconductor region such that the surface of the second semiconductor region is positioned lower than an interface between the first electrode and the interlayer insulating film;

forming a second electrode that contacts the second semiconductor region, the second electrode being adjacent to the first electrode via the insulating film formed on a sidewall of the trench; and

wherein the second semiconductor region is removed to a depth that is equal to or greater than 0.05 μm and equal to or less than 2 μm from the interface between the first electrode and the interlayer insulating film to the surface of the second semiconductor region.

Assignments (2)
MERGER AND CHANGE OF NAME Recorded Aug 26, 2011
From: FUJI ELECTRIC SYSTEMS CO., LTD. (FES); FUJI TECHNOSURVEY CO., LTD. (MERGER BY ABSORPTION)
To: FUJI ELECTRIC CO., LTD.
Reel/Frame 026970/0872 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 17, 2011
From: MOMOTA, SEIJI
To: FUJI ELECTRIC SYSTEMS CO., LTD.
Reel/Frame 025825/0590 →