Mirrored-gate cell for non-volatile memory
View Patent ↗A memory comprising at least one memory cell operationally connected to a bit line, a source line and a word line. The memory cell comprises a substrate having a first source contact, a second source contact, and a bit contact between the first source contact and the second source contact, a first transistor gate electrically connecting the first source contact and the bit contact and a second transistor gate electrically connecting the bit contact and the second source contact. The word line electrically connects the first transistor gate to the second transistor gate.
1. A memory comprising:
at least one column having at least one memory cell;
at least one row having at least the one memory cell, the at least one memory cell comprising:
a first source contact, a second source contact, and a first bit contact between the first source contact and the second source contact;
a first transistor gate spanning and electrically connecting the first source contact and the first bit contact; and
a second transistor gate spanning and electrically connecting the first bit contact and the second source contact;
a source line electrically connected to the first source contact and the second source contact of the at least one memory cell;
a bit line electrically connected to the first bit contact of the at least one memory cell;
a word line electrically connecting the first transistor gate and the second transistor gate; and
a first memory element electrically connecting the first bit contact and the bit line.
2. The memory according to claim 1 further comprising a second memory element electrically connecting the first source contact to the source line.
3. The memory according to claim 2 , wherein the second memory element is independently chosen from a programmable metallization cell or a phase change metallization cell.
4. The memory according to claim 1 , wherein the first memory element is a resistive element.
5. The memory according to claim 4 , wherein the resistive element is a programmable metallization cell or a phase change metallization cell.
6. The memory according to claim 1 , wherein the first memory element is connected epitaxially to the first bit contact.
7. The memory of claim 1 further comprising a second column and an insulation element between the first column and the second column, the second column having at least one memory cell.
8. The memory cell of claim 7 wherein the insulation element is a field oxide insulator.
9. The memory of claim 1 , wherein the word line comprises a first arm connected to a second arm, the first arm electrically connected to the first transistor gate and the second arm electrically connected to the second transistor gate.
10. The memory of claim 1 , the at least one memory cell being a first memory cell, with the column further comprising a second memory cell adjacent the first memory cell, the second memory cell comprising:
the second source contact, a third source contact, and a second bit contact between the second source contact and the third source contact;
a third transistor gate spanning and electrically connecting the second bit contact and the second source contact; and
a fourth transistor gate spanning and electrically connecting the third source contact and the second bit contact;
with a second word line electrically connecting the third transistor gate and the fourth transistor gate.
11. The memory of claim 10 , wherein the word line comprises a first arm connected to a second arm, the first arm electrically connected to the first transistor gate and the second arm electrically connected to the second transistor gate, and wherein the second word line comprises a third arm connected to a fourth arm, the third arm electrically connected to the third transistor gate and the fourth arm electrically connected to the fourth transistor gate.
12. The memory of claim 10 , the column further comprising a third memory cell adjacent the second memory cell and a fourth memory cell adjacent the third memory cell.
13. The memory of claim 10 , wherein each memory cell comprises an “n” number of bit contacts and “n+1” number of source contacts.
14. A memory comprising:
at least one column having at least one memory cell;
at least one row having at least the one memory cell, the at least one memory cell comprising:
a first source contact, a second source contact, and a bit contact between the first source contact and the second source contact;
a first transistor gate spanning and electrically connecting the first source contact and the bit contact; and
a second transistor gate spanning and electrically connecting the bit contact and the second source contact;
a source line electrically connected to the first source contact and the second source contact of the at least one memory cell;
a bit line electrically connected to the bit contact of the at least one memory cell;
a word line electrically connecting the first transistor gate and the second transistor gate;
a first memory element electrically connecting the bit contact and the bit line; and
a second memory element electrically connecting the first source contact to the source line.
15. The memory according to claim 14 , wherein the memory comprises a plurality of source contacts and a plurality of bit contacts.
16. The memory according to claim 15 , wherein each memory cell comprises an “n” number of bit contacts and “n+1” number of source contacts.
17. The memory according to claim 14 , wherein the memory comprises a plurality of memory elements, with each memory element electrically connecting a source contact to a source line or a bit contact to a bit line.
18. The memory according to claim 17 , wherein the plurality of memory elements are resistive elements.
19. The memory according to claim 18 , wherein the resistive elements are independently programmable metallization cells or phase change metallization cells.
20. A memory comprising:
at least one column having at least one memory cell;
at least one row having at least the one memory cell, the at least one memory cell comprising:
a first source contact, a second source contact, and a bit contact between the first source contact and the second source contact;
a first transistor gate spanning and electrically connecting the first source contact and the bit contact; and
a second transistor gate spanning and electrically connecting the bit contact and the second source contact;
a source line electrically connected to the first source contact and the second source contact of the at least one memory cell;
a bit line electrically connected to the bit contact of the at least one memory cell;
a word line electrically connecting the first transistor gate and the second transistor gate; and
a plurality of memory elements, with each memory element electrically connecting a source contact to a source line or a bit contact to a bit line, wherein each of the plurality of memory elements are connected epitaxially to its respective source or bit contact.