IP Library Granted Patent US 8,453,022
Granted Patent B2
US 8,453,022 · App. 12/596,450 · Granted May 28, 2013

Apparatus and methods for generating row-specific reading thresholds in flash memory

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Quick Facts
Patent No.
US 8,453,022
App. No.
12/596,450
Granted
May 28, 2013
Kind
B2
Abstract

A method for generating a set of at least one row-specific reading threshold for reading at least portions of pages of data within an erase sector of a flash memory device, the method comprising predetermining at least one initial reading threshold; performing the following steps for at least one current logical page: generating bit error characterizing information regarding at least one corresponding bit error within at least one cell representing at least a logical portion of at least one successfully reconstructed previous logical page; and computing at least one row-specific reading threshold based on said bit error characterizing information and on a previous threshold initially comprising said initial threshold and subsequently comprising a row-specific reading threshold computed for a successfully reconstructed previous logical page; and reading at least a portion of said current logical page using said at least one row-specific reading threshold.

Claims (36)

1. A method for generating a set of at least one row-specific reading threshold, the method comprising:

predetermining at least one initial reading threshold;

performing the following steps for at least one current logical page:

generating bit, error characterizing information regarding at least one corresponding bit error within at least one flash memory cell representing at least a logical portion of at least one successfully reconstructed previous logical page; and

computing each row-specific reading threshold out of at least one row-specific reading threshold based on said bit error characterizing information and on a previous threshold initially comprising an initial threshold out of the at least one initial reading threshold and subsequently comprising a row-specific reading threshold computed for a successfully reconstructed previous logical page; and

reading at least a portion of said current logical page, wherein the reading comprises comparing gate voltages of flash memory cells representing the at least portion of said current logical page to said at least one row-specific reading threshold.

2. The method according to claim 1 wherein said bit error characterizing information comprises identification of a reading threshold associated with the bit error.

3. The method according to claim 1 wherein said bit error characterizing information comprises a direction of the bit error.

4. The method according to claim 1 wherein a first number of threshold errors whose direction, with respect to said previous threshold, is from left to right is compared to a second number of threshold errors whose direction, with respect to said previous threshold, is from right to left, wherein the row-specific reading threshold depends upon at least one of the sign and magnitude of the difference between said first and second numbers of threshold errors.

5. The method according to claim 1 and also comprising: selecting a subset of rows within said erase sector; and identifying a set of logical pages residing within said subset of rows; and performing said generating, computing and reading for said set of logical pages and for less than all pages in said erase sector.

6. The method according to claim 5 and wherein said generating, computing and reading are performed only for said set of logical pages.

7. The method according to claim 1 wherein said previous threshold is corrected only if a number of bit errors per page is in a process of change of at least a predetermined magnitude.

8. The method according to claim 7 wherein said previous threshold is corrected only if a difference between a number of bit errors encountered during reconstruction of said current page and a number of bit errors occurring during reconstruction of at least one previous page is larger than a predetermined number.

9. The method according to claim 1 wherein said generating is performed for at least one CSB page residing in a row corresponding to an MSB page also residing in said row, based at least partly on values read from said MSB page.

10. The method according to claim 9 wherein said generating performed for said CSB page is based at least partly on values read on-the-fly from said MSB page.

11. The method according to claim 9 wherein said generating performed for said CSB page is based at least partly on stored values previously read from said MSB page.

12. The method according to claim 1 wherein said generating is performed for an LSB page residing in a row corresponding to an MSB and at least one CSB page also residing in said row, based at least partly on values read from at least one of said MSB and CSB pages.

13. The method according to claim 12 wherein said generating performed for said LSB page is based at least partly on values read on-the-fly from at least one of said MSB and CSB pages.

14. The method according to claim 12 wherein said generating performed for said LSB page is based at least partly on stored values previously read from at least one of said MSB and CSB pages.

15. A method for using flash memory to store data, the method comprising:

writing at least one page of data to said flash memory;

reading said at least one page of data from said flash memory using a set of reading thresholds;

generating bit error characterizing information regarding at least one corresponding bit error within at least one cell representing at least a logical portion of at least one successfully reconstructed previous logical page; and

detecting portions of said flash memory which suffer from read-disturb phenomenon based on said bit error characterizing information.

16. The method according to claim 15 wherein said bit error characterizing information comprises identification of a reading threshold which is associated with the bit error.

17. The method according to claim 15 wherein said bit error characterizing information comprises a direction of the bit error.

18. The method according to claim 15 wherein said detecting comprises detecting an overly large number of bit errors whose source is a reading threshold which is closest, within said set of reading thresholds, to zero voltage, and whose direction is from left to right.

19. A system for generating a set of at least one row-specific reading threshold for reading at least portions of pages of data within an erase sector of a flash memory device, the system comprising:

apparatus for predetermining at least one initial reading threshold;

a bit error analyzer operative, for at least one current logical page, to generate bit error characterizing information regarding at least one corresponding bit error within at least one cell of the flash memory device representing at least a logical portion of at least one successfully reconstructed previous logical page;

a bit error-based threshold generator operative to compute each row-specific reading threshold out of at least one row-specific reading threshold based on said bit error characterizing information and on a previous threshold initially comprising an initial threshold out of the at least one initial thresholds and subsequently comprising a row-specific reading threshold computed for a successfully reconstructed previous logical page; and

a flash memory cell reader operative to read at least a portion of said current logical page by comparing gate voltages of flash memory cells representing the at least portion of said current logical page to said at least one row-specific reading threshold.

20. A system for using flash memory to store data, the system comprising:

apparatus for writing in flash memory operative to write at least one page of data to the flash memory;

a bit error characterizing reader operative to read said at least one page of data from said flash memory using a set of reading thresholds, and to generate bit error characterizing information regarding at least one corresponding bit error within at least one cell representing at least a logical portion of at least one successfully reconstructed previous logical page; and

a bit error-based controller operative to detect portions of said flash memory which suffer from read-disturb phenomenon based on said bit error characterizing information.

Assignments (9)
MERGER Recorded Mar 3, 2023
From: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED; BROADCOM INTERNATIONAL PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 062952/0850 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 14, 2020
From: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
To: BROADCOM INTERNATIONAL PTE. LTD.
Reel/Frame 053771/0901 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EXECUTION DATE PREVIOUSLY RECORDED AT REEL: 047422 FRAME: 0464. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 6, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048883/0702 →
MERGER Recorded Oct 5, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047422/0464 →
RELEASE OF SECURITY INTEREST Recorded Jan 11, 2017
From: KREOS CAPITAL IV (EXPERT FUND) LIMITED
To: DENSBITS TECHNOLOGIES LTD.
Reel/Frame 041339/0921 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 27, 2016
From: DENSBITS TECHNOLOGIES LTD.
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 037622/0224 →
SECURITY INTEREST Recorded Mar 18, 2015
From: DENSBITS TECHNOLOGIES LTD.
To: KREOS CAPITAL IV (EXPERT FUND) LIMITED
Reel/Frame 035222/0547 →
SECURITY INTEREST Recorded Jul 30, 2014
From: DENSBITS TECHNOLOGIES LTD.
To: KREOS CAPITAL IV (EXPERT FUND) LIMITED
Reel/Frame 033444/0628 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 27, 2011
From: KATZ, MICHAEL
To: DENSBITS TECHNOLOGIES LTD.
Reel/Frame 026351/0951 →