High performance cryptography on chip multithreading processors

1. A method of processing a cipher using a chip multithreading (CMT) processor, the method comprising:

receiving a selection of a cipher, wherein the cipher is processed by executing a plurality of arithmetic logic unit operations on a chip multithreading processor;

determining lookup tables used during the execution of the plurality of arithmetic logic unit operations;

counting a number of arithmetic logic unit operations executed during processing of the selected cipher on the chip multithreading processor to determine an initial operation count;

increasing the size of at least one lookup table to thereby reduce a number of the lookup tables in order to improve processing the cipher by the chip multithreading processor, wherein the at least one lookup table is able to be stored in a processor cache located on a chip multithreading processor chip;

processing the selected cipher on the chip multithreading processor after increasing the size of the at least one lookup table;

counting the number of arithmetic logic unit operations executed during processing of the selected cipher on the chip multithreading processor with the increased at least one lookup table to determine an adjusted operation count;

comparing the initial operation count with the adjusted operation count to determine an operation count result; and

adjusting the size of the increased at least one lookup table based on the operation count result, wherein the increased at least one lookup table is able to be stored in a processor cache located on a chip multithreading processor chip after being adjusted.

2. The method of claim 1 wherein increasing comprises:

increasing the size of the at least one lookup table such that no lookup table is so large that it is unable to be stored in a processor cache located on a chip multithreading processor chip.

3. The method of claim 2 wherein receiving comprises:

receiving a selection of a Kasumi cipher, wherein the Kasumi cipher is performed by executing a plurality of arithmetic logic unit operations; and

wherein increasing comprises:

increasing the size of two lookup tables such that each of the two tables is able to be stored in a processor cache located on a chip multithreading processor chip.

4. The method of claim 1 comprising:

monitoring other operations being executed on the chip multithreading processor to produce an operation execution result; and

using the operation execution result to further adjust the size of the increased at least one lookup table, wherein the increased at least one lookup table is able to be stored in a processor cache located on a chip multithreading processor chip after being adjusted.

5. The method of claim 1 wherein determining comprises:

determining a plurality of initial lookup tables used during the execution of the plurality of arithmetic logic unit operations; and

wherein increasing comprises combining a plurality of initial lookup tables into a single lookup table, the single lookup table able to be stored in a processor cache located on a chip multithreading processor chip.

6. The method of claim 1 wherein determining comprises:

determining a plurality of initial lookup tables used during the execution of the plurality of arithmetic logic unit operations; and

wherein increasing comprises:

pre-computing additional operations to produce results; and

combining results into an initial lookup table, that lookup table able to be stored in a processor cache located on a chip multithreading processor chip.

7. A computer program product, stored on a non-transitory computer readable storage medium, to process a cipher using a chip multithreading (CMT) processor, the computer program product comprising:

computer program code for receiving a selection of a cipher, wherein the cipher is processed by executing a plurality of arithmetic logic unit operations on a chip multithreading processor;

computer program code for determining lookup tables used during the execution of the plurality of arithmetic logic unit operations;

computer program code for counting a number of arithmetic logic unit operations executed during processing of the selected cipher on the chip multithreading processor to determine an initial operation count;

computer program code for increasing the size of at least one lookup table to thereby reduce a number of the lookup tables in order to improve processing the cipher by the chip multithreading processor, wherein the at least one lookup table is able to be stored in a processor cache located on a chip multithreading processor chip;

computer program code for processing the selected cipher on the chip multithreading processor after increasing the size of the at least one lookup table;

computer program code for counting the number of arithmetic logic unit operations executed during processing of the selected cipher on the chip multithreading processor with the increased at least one lookup table to determine an adjusted operation count;

computer program code for comparing the initial operation count with the adjusted operation count to determine an operation count result; and

computer program code for adjusting the size of the increased at least one lookup table based on the operation count result, wherein the increased at least one lookup table is able to be stored in a processor cache located on a chip multithreading processor chip after being adjusted.

8. The computer program product of claim 7 wherein computer program code for increasing comprises:

computer program code for increasing the size of the at least one lookup table such that no lookup table is so large that it is unable to be stored in a processor cache located on a chip multithreading processor chip.

9. The computer program product of claim 7 comprising:

computer program code for monitoring other operations being executed on the chip multithreading processor to produce an operation execution result; and

computer program code for using the operation execution result to further adjust the size of the increased at least one lookup table, wherein the increased at least one lookup table is able to be stored in a processor cache located on a chip multithreading processor chip after being adjusted.

10. A computer system comprising:

a non-transitory computer readable memory;

a processor chip including a chip multithreading processor and a processor cache;

a communications interface;

an interconnect mechanism coupling the memory, the processor chip, and the communications interface, allowing communications there between;

wherein the memory is encoded with a cryptographic operations application, that when executed in the chip multithreading processor of the processor chip, processes a cipher by causing the computer system to perform the operations of:

receiving a selection of a cipher, wherein the cipher is processed by executing a plurality of arithmetic logic unit operations on a chip multithreading processor;

determining lookup tables used during the execution of the plurality of arithmetic logic unit operations;

counting a number of arithmetic logic unit operations executed during processing of the selected cipher on the chip multithreading processor to determine an initial operation count;

increasing the size of at least one lookup table to thereby reduce a number of the lookup tables in order to improve processing the cipher by the chip multithreading processor, wherein the at least one lookup table is able to be stored in a processor cache located on a chip multithreading processor chip;

processing the selected cipher on the chip multithreading processor after increasing the size of the at least one lookup table;

counting the number of arithmetic logic unit operations executed during processing of the selected cipher on the chip multithreading processor with the increased at least one lookup table to determine an adjusted operation count;

comparing the initial operation count with the adjusted operation count to determine an operation count result; and

adjusting the size of the increased at least one lookup table based on the operation count result, wherein the increased at least one lookup table is able to be stored in a processor cache located on a chip multithreading processor chip after being adjusted.

11. The computer system of claim 10 wherein increasing comprises:

increasing the size of the at least one lookup table such that no lookup table is so large that it is unable to be stored in a processor cache located on a chip multithreading processor chip.

12. The computer system of claim 10

wherein the computer system performs operations of:

monitoring other operations being executed on the chip multithreading processor to produce an operation execution result; and

using the operation execution result to further adjust the size of the increased at least one lookup table, wherein the increased at least one lookup table is able to be stored in a processor cache located on a chip multithreading processor chip after being adjusted.