Flash memory read performance
This disclosure describes techniques for reducing the number of data transmissions required to read an amount of data from multi-level-cell (MLC) flash memory. These techniques effectively increase the speed at which MLC flash memory can be read. This disclosure also describes techniques for reducing the amount of hardware and processing resources of a flash controller to read an amount of data. These techniques effectively increase the speed at which flash memory can be read by the flash controller without modifying conventional flash memories.
1. A flash controller comprising:
a first page memory configured to store a first reference bit corresponding to a first bit of a data value stored in a flash-memory cell;
a logic circuit configured to perform a logic operation on two or more additional reference bits to output a result that corresponds to a second bit of the data value stored in the flash-memory cell; and
a second page memory configured to store the result, wherein the flash controller is configured to determine the first bit and the second bit of the data value stored in the flash-memory cell by accessing the first page memory and the second page memory.
2. The flash controller as recited in claim 1 , wherein the result is inverted before being stored in the second page memory.
3. The flash controller as recited in claim 1 , wherein the first reference bit corresponds to a most-significant bit of a two-bit data value stored in the flash-memory cell, and wherein the result corresponds to a least-significant bit of the two-bit data value stored in the flash memory cell.
4. The flash controller as recited in claim 1 , wherein the logic circuit comprises an exclusive-or (XOR) gate, and wherein the logic operation comprises an XOR operation.
5. The flash controller as recited in claim 4 , further comprising:
an additional XOR gate configured to perform an additional XOR operation on four or more additional reference bits to output an additional result corresponding to a third bit of the data value stored in the flash-memory cell; and
a third page memory configured to store the additional result.
6. The flash controller as recited in claim 5 , wherein the first reference bit corresponds to a most-significant bit of a three-bit data value stored in the flash-memory cell, wherein the result corresponds to a middle bit of the three-bit data value stored in the flash memory cell, and wherein the additional result corresponds to a least-significant bit of the three bit-data value stored in the flash memory cell.
7. The flash controller as recited in claim 5 , wherein the result is inverted before being stored in the second page memory, and wherein the additional result is inverted before being stored in the third page memory.
8. The flash controller as recited in claim 1 , wherein the flash-memory cell is a single-level-cell (SLC) flash-memory cell or a multi-level-cell (MLC) flash-memory cell.
9. A method comprising:
receiving two or more reference bits at a flash controller, the two or more reference bits determined from applying two or more reference voltages to a flash-memory cell; and
determining, at the flash controller, a data bit based on the two or more reference bits, the determining the data bit comprising performing one or more exclusive-or (XOR) operations on the two or more reference bits or performing one or more exclusive-nor (XNOR) operations on the two or more reference bits.
10. The method as recited in claim 9 , wherein the data bit is a bit of a data value stored in the flash-memory cell.
11. The method as recited in claim 9 , wherein the data bit is an inverse of a bit of a data value stored in the flash-memory cell.
12. The method as recited in claim 9 , wherein determining a data bit comprises:
performing the one or more exclusive-or (XOR) operations on the two or more reference bits to produce a result; and
inverting the result to create the data bit.
13. The method as recited in claim 9 , further comprising:
receiving a given reference bit at the flash controller, the given reference bit not included in the two or more reference bits; and
storing the given reference bit at the flash controller, the given reference bit being the most-significant bit of a data value stored in the flash memory cell.
14. The method as recited in claim 13 , wherein the data bit is the least-significant bit of the data value stored in the flash memory cell.
15. The method as recited in claim 13 , wherein the data bit is the middle bit of the data value stored in the flash memory cell.
16. The method as recited in claim 9 , wherein the flash-memory cell is a single-level-cell (SLC) flash-memory cell or a multi-level-cell (MLC) flash-memory cell.
17. A system comprising:
a flash-memory cell configured to store a data value; and
a flash controller comprising:
a first page memory configured to store a first reference bit received from the flash-memory cell, the first reference bit corresponding to a first bit of the data value stored in the flash-memory cell;
a logic circuit configured to perform a logic operation on two or more additional reference bits received from the flash-memory cell and to output a result that corresponds to a second bit of the data value stored in the flash-memory cell; and
a second page memory configured to store the result, wherein the flash controller is configured to determine the first bit and the second bit of the data value stored in the flash-memory cell by accessing the first page memory and the second page memory.
18. The system as recited in claim 17 , wherein the first reference bit corresponds to a most-significant bit of a two-bit data value stored in the flash-memory cell, and wherein the result corresponds to a least-significant bit of the two-bit data value stored in the flash memory cell.
19. The system as recited in claim 17 , wherein the logic circuit comprises an exclusive-or (XOR) gate, wherein the logic operation comprises an XOR operation, and wherein the flash controller further comprises:
an additional XOR gate configured to perform an additional XOR operation on four or more additional reference bits to output an additional result corresponding to a third bit of the data value stored in the flash-memory cell; and
a third page memory configured to store the additional result.