Method for reducing spurious for a clock distribution system
A method for reducing spurious for a clock distribution system, the method including a) providing a system controller, b) providing clock distribution system, c) inputting characteristics of the clock distribution system in advance of operation thereof, d) calculating an expected level of the integer boundary spurious as a function of a fractional offset value, e) selecting an integer boundary solution based on the fractional offset value being within a preferred predetermined region, and f) programming the master clock subsystem and the one or more fractional synthesizers with the integer boundary solution, and g) repeating steps d) through f) as needed.
1. A method for reducing spurious for a clock distribution system, the method comprising:
a) providing a system controller;
b) providing a clock distribution system including:
a master clock subsystem responsive to an external reference signal configured to generate a master clock signal and one or more intermediate clock signals each at a sub-multiple of the master clock signal, and
one or more fractional synthesizers each responsive to one of the one or more intermediate clock signals and each configured to generate an output signal at a desired frequency from a wide range of possible output frequencies based on a command from the system controller;
c) inputting characteristics of the clock distribution system in advance of operation thereof;
d) calculating an expected level of the integer boundary spurious as a function of fractional offset value to select a preferred region of operation;
e) providing a desired frequency of the output signal of operation;
f) selecting an integer boundary solution based on the fractional offset value being within a preferred predetermined region; and
g) programming the master clock subsystem and the one or more fractional synthesizers with the integer boundary solution; and
h) repeating steps e) through g) as needed.
2. The method of claim 1 in which the external reference signal has a fixed frequency.
3. The method of claim 1 in which the characteristics of the clock distribution subsystem includes IB spurious levels and higher order IB Spurious levels over the operating range of the one or more fractional synthesizers at the typical spurious levels.
4. The method of claim 1 in which the characteristics of clock distribution subsystem include typical spurious rolloff rates of IB spurs or higher order IB spurs as the one or more fractional synthesizers is tuned away from an IB or a higher order IB.
5. The method of claim 1 in which the input characteristics of the clock distribution subsystem include a typical loop bandwidth of the one or more fractional synthesizers.
6. The method of claim 1 in which the input characteristics of the clock distribution subsystem include a reference clock signal synthesized by the master clock subsystem.
7. The method of claim 6 in which the reference clock signal has a fixed frequency.
8. The method of claim 1 in which the input characteristics of the clock distribution subsystem include a realizable range of M-divider settings of the master clock subsystem.
9. The method of claim 1 in which characteristics of the clock distribution subsystem include a realizable range of R-divider settings of the master clock subsystem and the one or more frequency synthesizers.
10. The method of claim 1 in which the input characteristics of the clock distribution subsystem include a minimum limit or a maximum limit of a fractional divider of each of the one or more fractional synthesizers.
11. The method of claim 1 in which the input characteristics of the clock distribution system include a minimum limit or a maximum limit of the values of the greatest common divisor of a frequency of the output signal and a phase detector frequency at the input to the one or more fractional synthesizers.
12. The method of claim 1 in which the input characteristics of the clock distribution system include specific integer parts of the values of the fractional divider to be excluded.
13. The method of claim 1 in which the input characteristics of the clock distribution system include a minimum limit or maximum limit of the intermediate clock frequency at the input to the one or more fractional synthesizers.
14. The method of claim 1 in which the input characteristics of the clock distribution system include a minimum limit or a maximum limit of a phase detector clock frequency at the input to the one or more fractional synthesizers.
15. The method of claim 1 in which the input characteristics of the clock distribution system include the one or more fractional synthesizers having a fixed modulus.
16. The method of claim 1 in which the input characteristics of the clock distribution system include minimum spurious levels of IB spurs or higher order IB spurs as each of the one or more fractional synthesizers is tuned away from an IB or a higher order IB.
17. The method of claim 1 in which the input characteristics of the clock distribution system include allowable values of a fractional divider of the one or more fractional synthesizers.
18. The method of claim 1 in which the input characteristics of the clock distribution system include a minimum limit or a maximum limit of the frequency of a voltage controlled oscillator for the one or more fractional synthesizers.
19. The method of claim 1 in which the input characteristics of the clock distribution system include available values of division for a divider at the output to the one or more fractional synthesizers.
20. A method for reducing spurious for a clock distribution system, the method comprising:
a) providing a system controller;
b) providing a clock distribution system including:
a master clock subsystem responsive to an external reference signal configured to generate a master clock signal and one or more intermediate clock signals each at a sub-multiple of the master clock signal, and
one or more fractional synthesizers each responsive to one of the one or more intermediate clock signals and each configured to generate an output signal at a desired frequency from a wide range of possible output frequencies based on a command from the system controller;
c) inputting characteristics of the clock distribution system in advance of operation thereof;
d) providing a desired operating frequency of the output signal;
e) calculating possible candidate frequencies of the one or more intermediate clock signals;
f) calculating possible candidate frequencies of a phase detector of each of said one or more fractional synthesizers;
g) calculating the frequency offset from the nearest integer boundary (IB) of each of said candidate frequencies;
h) calculating integer and fractional parts of the output signal for each of the candidate frequencies;
i) rejecting any candidate frequencies outside of an acceptable range of said characteristics of the clock distribution system;
j) calculating an expected level of the integer boundary spurious for each remaining candidate frequency;
k) if any of said candidate frequencies are an integer boundary solution, select that candidate frequency solution, otherwise, select a candidate frequency solution that generates the lowest expected level of the integer boundary spurious;
l) programming the master clock subsystem and the one or more fractional synthesizers with the candidate frequency solution; and
m) repeating steps d) through l) as needed.