Semiconductor device

1. A device comprising:

first, second and third power supply lines supplied respectively with first, second and third power voltages that are different from one another;

first and second input terminals and an output terminal;

an output circuit coupled to the first power supply line, the first and second input terminals and the output terminal;

a first inverter including an input node coupled to the first input terminal and an output node coupled to the second input terminal;

a first transistor coupled in series to the first inverter between the second and third power supply lines, the first transistor being rendered non-conductive to deactivate the first inverter and conductive to activate the first inverter; and

a control circuit configured to prevent the output terminal from being brought into an electrical floating state during deactivation of the first inverter:

wherein the first power supply line is continuously supplied with the first voltage during both activation and deactivation of the first inverter.

2. The device as claimed in claim 1 , wherein the output terminal continuously takes the first power voltage during the deactivation of the first inverter.

3. The device as claimed in claim 1 , wherein the first input terminal is continuously fixed at one of the second and third power voltages during the deactivation of the first inverter.

4. A device comprising:

first, second and third power supply lines supplied respectively with first, second and third power voltages that are different from one another;

first and second input terminals and an output terminal;

an output circuit coupled to the first power supply line, the first and second input terminals and the output terminal;

a first inverter including an input node coupled to the first input terminal and an output node coupled to the second input terminal;

a first transistor coupled in series to the first inverter between the second and third power supply lines, the first transistor being rendered non-conductive to deactivate the first inverter; and

a second inverter including an input node coupled to the first input terminal and an output node coupled to the second input terminal.

5. The device as claimed in claim 4 , wherein the second inverter is greater in threshold voltage than the first inverter.

6. The device as claimed in claim 5 , wherein the output circuit comprises an intermediate node, a third transistor coupled between the first power supply line and the output terminal and including a gate coupled to the intermediate node, a fourth transistor coupled between the first power supply line and the intermediate node and including a gate coupled to the output terminal, a fifth transistor coupled between the output terminal and the second input terminal, and a sixth transistor coupled between the intermediate node and the first input terminal.

7. The device as claimed in claim 6 , wherein the fifth transistor includes a gate coupled to the first input terminal, and the sixth transistor includes a gate coupled to the second input terminal.

8. The device as claimed in claim 5 , wherein the device further comprises a fourth power supply line supplied with a fourth power voltage that is different from each of the first, second and third power voltages, and the output circuit comprises first and second intermediate nodes, a third transistor coupled between the first power supply line and the output terminal and including a gate coupled to the first intermediate node, a fourth transistor coupled between the first power supply line and the first intermediate node and including a gate coupled to the output terminal, a fifth transistor coupled between the first intermediate node and the second input terminal and including a gate coupled to the first input terminal, a sixth transistor coupled between the output terminal and the fourth power supply line and including a gate coupled to the second intermediate node, a seventh transistor coupled between the second intermediate node and the fourth power supply line and including a gate coupled to the output terminal, and an eighth transistor coupled between the second intermediate node and the second input terminal and including a gate coupled to the first input terminal.

9. The device as claimed in claim 4 , wherein the device further comprises a third inverter including an input node supplied with a signal and an output node coupled to the first input terminal, a second transistor coupled in series to the third inverter between the second and third power supply lines and rendered non-conductive to deactivate the third inverter, and a fourth inverter including an input node coupled to the input node of the third inverter and an output node coupled to the first input terminal.

10. The device as claimed in claim 9 , wherein the second inverter is greater in threshold voltage than the first inverter and the fourth inverter is greater in threshold voltage than the third inverter.

11. A device comprising:

first, second and third power supply lines supplied respectively with first, second and third power voltages that are different from one another;

first and second input terminals and an output terminal;

an output circuit coupled to the first power supply line, the first and second input terminals and the output terminal;

a first inverter including an input node coupled to the first input terminal and an output node coupled to the second input terminal;

a first transistor coupled in series to the first inverter between the second and third power supply lines, the first transistor being rendered non-conductive to deactivate the first inverter; and

a control circuit configured to prevent the output terminal from being brought into an electrical floating state during deactivation of the first inverter;

wherein the control circuit comprises a latch circuit.

12. The device as claimed in claim 11 , wherein the output circuit comprises an intermediate node, a second transistor coupled between the first power supply line and the output terminal and including a gate coupled to the intermediate node, a third transistor coupled between the first power supply line and the intermediate node and including a gate coupled to the output terminal, a fourth transistor coupled between the output terminal and the second input terminal, and a fifth transistor coupled between the intermediate node.

13. The device as claimed in claim 12 , wherein the latch circuit comprises a sixth transistor coupled between the output terminal and the third power supply line and including a gate coupled to the intermediate node and a seventh transistor coupled between the intermediate node and the third power supply line and including a gate coupled to the output terminal.

14. The device as claimed in claim 13 , wherein the device further comprises a second inverter including an input node supplied with a signal and an output node coupled to the first input terminal and an eighth transistor coupled in series to the second inverter between the second and third power supply lines, the eighth transistor being rendered non-conductive to deactivate the second inverter.

15. The device as claimed in claim 13 , wherein the latch circuit further comprises an eighth transistor inserted between the sixth transistor and the third power supply line and a ninth transistor inserted between the seventh transistor and the third power supply line, each of the eighth and ninth transistors being rendered conductive when the first transistor is rendered non-conductive.

16. The device as claimed in claim 12 , wherein the latch circuit comprises a second inverter including an input node coupled to the output terminal, a third inverter including an input node coupled to the intermediate node, a first transfer gate coupled between an output node of the second inverter and first input terminal, and a second transfer gate coupled between an output node of the third inverter and the second input terminal, each of the first and second transfer gates being rendered open when the first transistor being rendered non-conductive.

17. The device as claimed in claim 12 , wherein the fourth transistor includes a gate coupled to the first input terminal, and the fifth transistor includes a gate coupled to the second input terminal.

18. The device as claimed in claim 11 , wherein the latch circuit including first and second power nodes coupled respectively to the second and third power supply lines and first and second input/output nodes coupled respectively to the first and second input terminals, and the device further comprises a second inverter including an input node supplied with a signal and an output node coupled to the first input terminal and a second transistor coupled in series to the second inverter between the second and third power supply lines, the second transistor being rendered non-conductive to deactivate the second inverter.

19. The device as claimed in claim 18 , wherein the fourth transistor includes a gate coupled to the first input terminal, and the fifth transistor includes a gate coupled to the second input terminal.

20. The device as claimed in claim 11 , wherein the latch circuit includes second and third inverters coupled respectively to first and second input/output nodes, an input node of the second inverter coupled to the first input/output node, an output node of the second inverter coupled to the second input/output node, an input node of the third inverter coupled to the second input/output node, and an output node of the third inverter coupled to the first input/output node.