IP Library Granted Patent US 8,703,393
Granted Patent B1
US 8,703,393 · App. 13/155,299 · Granted Apr 22, 2014

Method for fabricating a circuit

Inventor: Krishnakumar Mani (Santa Clara, CA)
Assignee: MagSil Corporation
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Quick Facts
Patent No.
US 8,703,393
App. No.
13/155,299
Granted
Apr 22, 2014
Kind
B1
Abstract

A method for fabricating a circuit, by defining a first set of resist features on a substrate and corresponding to a first mask layout, followed by defining a second set of resist features on the substrate corresponding to a second mask layout, wherein the second set adds to the first set for rectifying an error in either mask layout. In another aspect, the method is by defining a first set of resist features on a substrate and corresponding to a first mask layout that has an error, etching the substrate while the first set protects selected regions, defining a second set of resist features on the substrate and corresponding to a second mask layout, followed by etching the substrate to selectively remove portions of the selected regions for rectifying the error.

Claims (14)

1. A method for fabricating a circuit, said method comprising:

defining a first set of resist feature(s) on a partially processed substrate and corresponding to a first mask layout, wherein said first mask layout has an error;

etching said substrate while said first set protects first selected region(s) on said substrate;

stripping said first set;

defining a second set of resist feature(s) on said substrate and corresponding to a second mask layout;

etching said substrate while said second set protects second selected region(s) on said substrate, said etching being to selectively remove portion(s) of said first selected region(s) on said substrate and to form void(s) therein for rectifying said error; and

processing for at least partially filling said void(s) with a dielectric material.

2. The method of claim 1 , wherein said error causes two lines of said circuit on said substrate to be connected instead of being disconnected.

3. The method of claim 1 , wherein said first selected region(s) is/are in a metallization layer.

4. The method of claim 1 , wherein said substrate originates from one of the following:

a) a semiconductor wafer,

b) a lithium niobate wafer and

c) a silicon on insulator (SOI) wafer.

5. The method of claim 1 , wherein both of said first and second sets are defined by positive-tone photoresists.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 11, 2014
From: MAGSIL CORPORATION
To: III HOLDINGS 1, LLC
Reel/Frame 032657/0837 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 8, 2011
From: MANI, KRISHNAKUMAR
To: MAGSIL CORPORATION
Reel/Frame 026406/0047 →