IP Library Granted Patent US 8,725,921
Granted Patent B2
US 8,725,921 · App. 13/553,519 · Granted May 13, 2014

Virtual multi-processor system

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Quick Facts
Patent No.
US 8,725,921
App. No.
13/553,519
Granted
May 13, 2014
Kind
B2
Abstract

A virtual multi-processor system includes a plurality of logic processors. Moreover, the virtual multi-processor system includes a logic processor controller configured to allocate a time slice to each of the logic processors to control the logic processors so that the logic processors sequentially run in a time-sharing manner. When a request for interrupt processing occurs, an external interrupt controller performs control so that a logic processor that has a time slice within which the interrupt processing is possible and that runs next executes the interrupt processing.

Claims (12)

1. A virtual multi-processor system comprising:

a plurality of logic processors;

a logic processor controller configured to allocate a time slice to each of the logic processors to control the logic processors so that the logic processors sequentially run in a time-sharing manner;

an interrupt handler processing-time table; and

an external interrupt controller configured to, when a request for an interrupt processing occurs, acquire interrupt processing time corresponding to the interrupt processing from the interrupt handler processing-time table, and then allow one of the logic processors that has a time slice longer than the interrupt processing time and that runs next to execute the interrupt processing,

wherein when time for the interrupt processing is longer than a remaining time slice of a currently running logic processor, the external interrupt controller changes the remaining time slice to zero via the logic processor controller, and allows the logic processor that runs next to execute the interrupt processing.

2. A virtual multi-processor system comprising:

a plurality of logic processors;

a logic processor controller configured to allocate a time slice to each of the logic processors to control the logic processors so that the logic processors sequentially run in a time-sharing manner;

an interrupt handler processing-time table; and

an external interrupt controller configured to, when a request for an interrupt processing occurs, acquire interrupt processing time corresponding to the interrupt processing from the interrupt handler processing-time table,

wherein when time for the interrupt processing is longer than a remaining time slice of a currently running logic processor, the external interrupt controller changes the remaining time slice via the logic processor controller to be longer than or equal to the time for the interrupt processing, and allows the currently running logic processor to execute the interrupt processing.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 25, 2015
From: PANASONIC CORPORATION
To: SOCIONEXT INC.
Reel/Frame 035294/0942 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 5, 2012
From: TAKEUCHI, AKIRA
To: PANASONIC CORPORATION
Reel/Frame 029080/0683 →