Differential serial interface for supporting a plurality of differential serial interface standards

1. An active capacitor multiplying circuit, comprising:

a clock synthesis loop filter of at least second order, wherein the clock synthesis loop filter comprises a series combination of a first resistor and a first capacitor, and wherein the series combination of the first resistor and the first capacitor is coupled between a first charge pump interface and ground, and wherein the clock synthesis loop filter further comprises a second capacitor coupled between the first charge pump interface and the ground;

a capacitor multiplying loop filter comprising a second capacitor coupled between a second charge pump interface and the ground, wherein the capacitor multiplying loop filter further comprises a second resistor coupled to the second charge pump interface and the second charge pump interface is coupled to the first charge pump interface; and

an operational amplifier, driven by the first capacitor, for driving the second resistor, wherein a voltage presented at the first charge pump interface drives a voltage controlled oscillator (VCO).

2. The active capacitor multiplying circuit of claim 1 , wherein capacitance of the first capacitor is magnified by a factor, wherein the factor comprises a difference between a first current across the first charge pump interface and a second current across the second charge pump interface.

3. The active capacitor multiplying circuit of claim 2 wherein the factor comprises a magnification value less than or equal to twenty.

4. The active capacitor multiplying circuit of claim 1 , wherein the operational amplifier is configured as a follower amplifier.

5. The active capacitor multiplying circuit of claim 1 wherein the first capacitor and the second capacitor are either i) concurrently charging or ii) concurrently discharging.