Logical Verification Apparatus and Method

1. A logical verification apparatus, comprising:

a processor; and

a storage part configured to store description data which describe an operation of a verification subject circuit,

a display part configured to display a result from verifying the verification subject circuit by using a logical simulation by the processor,

wherein the processor performs a logical verification process including:

deriving connection relationships pertinent to an input/output for each of a plurality of logic circuits in the verification subject circuit based on connection information of the verification subject circuit acquired from the description data in the storage part;

determining a first priority used for verifying the plurality of logic circuits by using the logic simulation based on the connection relationships being derived, in which the first priority is determined by acquiring a first number of first influenced logic circuits other than a first logic circuit when the first logic circuit is modified, in the plurality of the logic circuits;

extracting a plurality of related I/F circuits, which are related to input paths to each of the logic circuits and are interface parts between the verification subject circuit and an outside of the verification subject circuit, based on the connection information; and

determining a second priority used for verifying the plurality of related I/F circuits by the logical simulation based on the first priority;

displaying the first priority and the second priority at the display part;

inputting a priority order of a verification determined based on the first priority and the second priority being displayed at the display part, and verification items of the verification using the logical simulation; and

verifying the verification subject circuit by the logical simulation based on the priority order being input.

2. The logical verification apparatus as claimed in claim 1 , wherein in the verification process, the processor creates a connection count list in the storage part by extracting input information and output information for each of the plurality of logic circuits from the description data, wherein

the input information indicates a plurality of input signals to input to the plurality of logic circuits and a number of the plurality of input signals, and

the output information indicates a plurality of destination logic circuits to be output destinations of the logics and a number of the plurality of destination logics.

3. The logical verification apparatus as claimed in claim 2 , wherein in the logical verification process, the processor

counts a plurality of post-logic circuits connected to a first post-stage of outputs of a logic circuit for each of the plurality of logic circuits by referring to the connection count list from the storage part, and

determines the first priority based on a post-logic count result.

4. The logical verification apparatus as claimed in claim 2 , wherein in the logical verification process, the processor

counts a plurality of signals being combined with inputs of the plurality of logic circuits by referring to the connection count list for each of the plurality of logic circuits from the storage part, and

determines the first priority based on a signal count result.

5. The logical verification apparatus as claimed in claim 2 , wherein in the logical verification process, the processor

extracts input paths of signals to each of the plurality of logic circuits by referring to the connection count list from the storage, and

creates a list which indicates a plurality of modified logic circuits and, the input signals and the logics included in the related I/F circuits driving the modified logic circuits by comparing the input paths before and after the description data are modified.

6. The logical verification apparatus as claimed in claim 2 , wherein in the logical verification process, the processor

extracts the plurality of related I/F circuits related to the logic circuit by tracing back connections at an input side of the logic with respect to each of the plurality of logic circuits described in the description data based on the connection information acquired from the description data stored in the storage part, and

determines the second priority based on a total value acquired by accumulating values of the first priority of the logics being driven a plurality of by extracted related I/F circuits.

7. The logical verification apparatus as claimed in claim 1 , further comprising

acquiring, based on the connection relationships, a second number of second influenced logic circuits other than a second logic circuit when the second logic circuit different from the first logic circuit is modified, in the plurality of the logic circuits,

wherein the first priority is determined based on the first number and the second number.

8. A logical verification method performed in a computer, the method comprising:

acquiring, by the computer, connection information from description data which describe an operation of a verification subject circuit and are stored in a storage part;

deriving, by the computer, connection relationships pertinent to an input/output for each of a plurality of logic circuits in the verification subject circuit based on connection information of the verification subject circuit acquired from the description data in the storage part;

determining, by the computer, a first priority used for verifying the plurality of logic circuits by using the logical simulation based on the connection relationships being derived, in which the first priority is determined by acquiring a first number of first influenced logic circuits other than a first logic circuit when the first logic circuit is modified, in the plurality of the logic circuits;

extracting, by the computer, a plurality of related I/F circuits, which are related to input paths to each of the plurality of logic circuits and are interface parts between the verification subject circuit and an outside of the verification subject circuit, based on the connection information;

determining, by the computer, a second priority used for verifying the plurality of related I/F circuits by the logical simulation based on the first priority;

displaying, by the computer, the first priority and the second priority at a display part;

inputting, by the computer, a priority order of a verification determined based on the first priority and the second priority being displayed at the display part, and verification items of the verification using the logical simulation; and

verifying, by the computer, the verification subject circuit by the logical simulation based on the priority order being input.

9. A non-transitory computer-readable recording medium storing a program which, when executed by a computer, causes the computer to perform a logical verification process, the process comprising:

acquiring, by the computer, connection information from description data which describe an operation of a verification subject circuit and are stored in a storage part;

deriving, by the computer, connection relationships pertinent to an input/output for each of a plurality of logic circuits in the verification subject circuit based on connection information of the verification subject circuit acquired from the description data in the storage part;

determining, by the computer, a first priority used for verifying the plurality of logic circuits by using the logical simulation based on the connection relationships being derived, in which the first priority is determined by acquiring a first number of first influenced logic circuits other than a first logic circuit when the first logic circuit is modified, in the plurality of the logic circuits;

extracting, by the computer, a plurality of related I/F circuits, which are related to input paths to each of the circuits and are interface parts between the verification subject circuit and an outside of the verification subject circuit, based on the connection information;

determining, by the computer, a second priority used for verifying the related I/F circuits by the logical simulation based on the first priority;

displaying, by the computer, the first priority and the second priority at a display part;

inputting, by the computer, a priority order of a verification determined based on the first priority and the second priority being displayed at the display part, and verification items of the verification using the logical simulation; and

verifying, by the computer, the verification subject circuit by the logical simulation based on the priority order being input.