Method to construct a 3D semiconductor device
View Patent ↗A method to construct a semiconductor device, the method including: forming a first layer including mono-crystallized semiconductor and first logic circuits; forming a second layer including a mono-crystallized semiconductor layer, the second layer overlying the first logic circuits; forming transistors on the second layer; forming connection paths from the second transistors to the first transistors, where the connection paths include a through layer via of less than 200 nm diameter; and connecting the first logic circuits to an external device using input/output (I/O) circuits, the input/output (I/O) circuits are constructed on the second mono-crystallized semiconductor layer.
1. A method to construct a semiconductor device, the method comprising:
forming a first layer comprising mono-crystallized semiconductor and first logic circuits;
forming a second layer comprising a mono-crystallized semiconductor layer, said second layer overlying said first logic circuits;
forming transistors on said second layer;
forming connection paths from said second transistors to said first transistors,
wherein said connection paths comprise a through layer via of less than 200 nm diameter; and
connecting said first logic circuits to an external device using input/output (I/O) circuits, said input/output (I/O) circuits are constructed on said second mono-crystallized semiconductor layer.
2. The method according to claim 1 ,
wherein said first logic circuits comprise copper or aluminum interconnect, and
wherein a plurality of said transistors are connected to form second logic circuits.
3. The method according to claim 1 ,
wherein said first logic circuits comprises copper or aluminum interconnect, and
wherein at least one of said transistors is a horizontally oriented transistor.
4. The method according to claim 1 , further comprising:
etching at least a portion of said transistors in a customization step of a generic structure.
5. The method according to claim 1 ,
wherein said semiconductor device comprises a circuit that provides a wireless connection to a device that is external to said semiconductor device.
6. The method according to claim 1 ,
wherein said forming transistors comprises optical annealing.
7. The method according to claim 1 ,
wherein said forming transistors comprises gate replacement.
8. A method to construct a semiconductor device, the method comprising:
forming a first layer comprising mono-crystallized semiconductor and first logic circuits;
forming a second layer comprising a mono-crystallized semiconductor layer, said second layer overlying said first logic circuits;
forming transistors on said second layer;
forming connection paths from said second transistors to said first transistors,
wherein said connection paths comprise a through layer via of less than 200 nm diameter; and
connecting said first logic circuits to an external device using input/output (I/O) circuits, said input/output (I/O) circuits are constructed on said second mono-crystallized semiconductor layer,
wherein said input/output (I/O) circuits comprise a SerDes circuit.
9. The method according to claim 8 ,
wherein said first logic circuits comprise copper or aluminum interconnect, and
wherein a plurality of said transistors are connected to form second logic circuits.
10. The method according to claim 8 ,
wherein said semiconductor device comprises a circuit that provides a wireless connection to a device that is external to said semiconductor device.
11. The method according to claim 8 , further comprising:
etching at least a portion of said transistors in a customization step of a generic structure.
12. The method according to claim 8 ,
wherein said forming transistors comprises optical annealing.
13. The method according to claim 8 ,
wherein said forming transistors comprises gate replacement.
14. A method to construct a semiconductor device, the method comprising:
forming a first layer comprising mono-crystallized semiconductor and first logic circuits;
forming a second layer comprising a mono-crystallized semiconductor layer, said second layer overlying said first logic circuits;
forming transistors on said second layer;
forming connection paths from said second transistors to said first transistors,
wherein said connection paths comprise a through layer via of less than 200 nm diameter,
wherein said transistors are connected to form second logic circuits, and
wherein said second logic circuits comprise a scan chain.
15. The method according to claim 14 ,
wherein said first logic circuits comprise copper or aluminum interconnect.
16. The method according to claim 14 ,
wherein said first logic circuits comprises copper or aluminum interconnect, and
wherein at least one of said transistors is a horizontally oriented transistor.
17. The method according to claim 14 , further comprising:
etching at least a portion of said transistors in a customization step of a generic structure.
18. The method according to claim 14 ,
wherein said semiconductor device comprises a circuit that provides a wireless connection to an external device.
19. The method according to claim 14 , further comprising:
connecting said first logic circuits to an external device using input/output (I/O) circuits, said input/output (I/O) circuits are constructed on said second mono-crystallized semiconductor layer.
20. The method according to claim 14 ,
wherein said forming transistors comprises gate replacement.