Multilayer interconnects with an extension part

1. A semiconductor device comprising:

a stacked via structure including:

a plurality of first vias formed over a substrate,

a first interconnect formed on the plurality of first vias,

a plurality of second vias formed on the first interconnect, and

a second interconnect formed on the plurality of second vias,

wherein one of the plurality of first vias closest to one end part of the first interconnect and one of the plurality of second vias closest to the one end part of the first interconnect at least partially overlap with each other as viewed in plane, and

the first interconnect has a first extension part extending from a position of an end of the one of the plurality of first vias closest to the one end part of the first interconnect toward the one end part of the first interconnect,

wherein the first interconnect has a second extension part extending from the position of the end of the one of the plurality of first vias closest to the one end part of the first interconnect in a direction crossing an extension direction of the first extension part.

2. The semiconductor device of claim 1 , further comprising:

a third interconnect formed above the substrate and below the first interconnect.

3. The semiconductor device of claim 1 , wherein

the substrate is connected to the first interconnect through the plurality of first vias.

4. The semiconductor device of claim 1 , wherein a length of the second extension part is more than six times as long as a via width of the one of the plurality of first vias.

5. The semiconductor device of claim 1 , further comprising:

one or more upper interconnects formed above the second interconnect; and

an upper via electrically connecting the second interconnect and the upper interconnects together and at least partially overlapping with the plurality of first vias and the plurality of second vias as viewed in the plane.

6. The semiconductor device of claim 5 , wherein of the second interconnect and the upper interconnects, at least one of intermediate interconnects other than an uppermost interconnect has a third extension part extending from a position of an end of the second via or the upper via toward an end part of each of the intermediate interconnects.

7. The semiconductor device of claim 5 , wherein

the plurality of first vias are connected to a lowermost interconnect, and

the upper via connected to the uppermost interconnect of the upper interconnects has a via width which is more than twice as large as the via width of the one of the plurality of first vias.

8. The semiconductor device of claim 5 , wherein

the plurality of first vias are connected to a lowermost interconnect, and

the number of the upper via connected to an uppermost interconnect of the upper interconnects is less than the number of the plurality of first vias.

9. The semiconductor device of claim 1 , wherein

the second interconnect is an uppermost interconnect,

the plurality of first vias are connected to a lowermost interconnect, and

a via width of each of the plurality of second vias is more than twice as large as a via width of each of the plurality of first vias.

10. The semiconductor device of claim 1 , wherein a width of the first interconnect is substantially equal to a width of the second interconnect.

11. The semiconductor device of claim 1 , wherein the first extension part extends from the position of the end of the one of the plurality of first vias closest to the one end part of the first interconnect toward the one end part of the first interconnect so as to have a length which is more than eight times as long as the via width of the one of the plurality of first vias.

12. The semiconductor device of claim 1 , wherein the one of the plurality of first vias closest to the one end part of the first interconnect is positioned in a downstream end part of a current flow path for current flowing in the first interconnect in an extension direction thereof.

13. The semiconductor device of claim 1 , wherein

the plurality of second vias connected to the second interconnect are not connected to the first extension part.

14. The semiconductor device of claim 1 , wherein the first interconnect has a length which is more than six times as long as a via width of the one of the plurality of first vias.

15. A semiconductor device comprising:

a stacked via structure including:

a plurality of first vias formed over a substrate,

a first interconnect formed on the plurality of first vias,

a plurality of second vias formed on the first interconnect, and

a second interconnect formed on the plurality of second vias,

wherein one of the plurality of first vias closest to one end part of the first interconnect and one of the plurality of second vias closest to the one end part of the first interconnect at least partially overlap with each other as viewed in plane, and

the first interconnect has a first extension part extending from a position of an end of the one of the plurality of first vias closest to the one end part of the first interconnect toward the one end part of the first interconnect,

further comprising:

a first dummy via formed on the first extension part; and

a first dummy interconnect which is formed on the first dummy via in an interconnect layer identical to that of the second interconnect and in which a substantial current flow path is not formed during an operation.

16. The semiconductor device of claim 15 , further comprising:

at least one upper dummy interconnect formed above the first dummy interconnect; and

an upper dummy via formed between the first dummy interconnect and the at least one upper dummy interconnect.

17. The semiconductor device of claim 15 , wherein the first interconnect has a length which is more than six times as long as a via width of the one of the plurality of first vias.

18. A semiconductor device comprising:

a stacked via structure including:

a plurality of first vias formed over a substrate,

a first interconnect formed on the plurality of first vias,

a plurality of second vias formed on the first interconnect, and

a second interconnect formed on the plurality of second vias,

wherein one of the plurality of first vias closest to one end part of the first interconnect and one of the plurality of second vias closest to the one end part of the first interconnect at least partially overlap with each other as viewed in plane, and

the first interconnect has a first extension part extending from a position of an end of the one of the plurality of first vias closest to the one end part of the first interconnect toward the one end part of the first interconnect,

further comprising:

a third interconnect formed above the substrate and below the first interconnect,

a first dummy via formed below the first extension part; and

a first dummy interconnect which is formed below the first dummy via in an interconnect layer identical to that of the third interconnect and in which a substantial current flow path is not formed during an operation.

19. The semiconductor device of claim 18 , wherein the first interconnect has a length which is more than six times as long as a via width of the one of the plurality of first vias.

20. A semiconductor device comprising:

a stacked via structure including:

a plurality of first vias formed over a substrate,

a first interconnect formed on the plurality of first vias,

a plurality of second vias formed on the first interconnect, and

a second interconnect formed on the plurality of second vias,

wherein one of the plurality of first vias closest to one end part of the first interconnect and one of the plurality of second vias closest to the one end part of the first interconnect at least partially overlap with each other as viewed in plane, and

the first interconnect has a first extension part extending from a position of an end of the one of the plurality of first vias closest to the one end part of the first interconnect toward the one end part of the first interconnect,

wherein the substrate is connected to the first interconnect through the plurality of first vias, and

further comprising:

an impurity-containing diffusion layer formed in the substrate and connected to the plurality of first vias;

an impurity-containing dummy diffusion layer formed in the substrate and electrically separated from the diffusion layer; and

a first dummy via directly connecting the first extension part and the dummy diffusion layer together.

21. The semiconductor device of claim 20 , wherein the first interconnect has a length which is more than six times as long as a via width of the one of the plurality of first vias.

22. A semiconductor device comprising:

a stacked via structure including:

a plurality of first vias formed over a substrate,

a first interconnect formed on the plurality of first vias,

a second via formed on the first interconnect, and

a second interconnect formed on the second via,

wherein the first interconnect has an extension part extending from a position of an end of one of the plurality of first vias closest to one end part of the first interconnect toward the one end part of the first interconnect and having a length which is more than six times as long as a via width of the one of the plurality of first vias, and

wherein the first interconnect has a second extension part extending from the position of the end of the one of the plurality of first vias closest to the one end part of the first interconnect in a direction crossing an extension direction of the first extension part.