Polysilicon thin film transistor array panel and manufacturing method thereof
View Patent ↗A method of manufacturing a thin film transistor array panel is provided, which includes: depositing an amorphous silicon layer on an insulating substrate; converting the amorphous silicon layer to a polysilicon layer by a plurality of laser shots using a mask; forming a gate insulating layer on the polysilicon layer; forming a plurality of gate lines on the gate insulating layer; forming a first interlayer insulating layer on the gate lines; forming a plurality of data lines on the first interlayer insulating layer; forming a second interlayer insulating layer on the data lines; and forming a plurality of pixel electrodes on the second interlayer insulating layer, wherein the mask comprises a plurality of transmitting areas and a plurality of blocking areas arranged in a mixed manner.
1. A silicon crystallization method comprising:
depositing an amorphous silicon layer on an insulating substrate;
melting the amorphous silicon layer by illuminating a laser beam through a mask including a plurality of transmitting areas and a plurality of blocking areas; and
forming a crystallized silicon layer by crystallizing the melted amorphous silicon layer,
wherein a first outline of a first transmitting area of the transmitting areas has a stepwise shape and the first outline having the stepwise shape is formed as only one of an upper outline and a lower outline of the first transmitting area,
wherein grain boundaries of the crystallized silicon layer do not coincide with each other between the first outline of the first transmitting area and a second outline of the first transmitting area opposite the first outline,
wherein the grain boundaries form central transverse lines between the first outline of the first transmitting area and the second outline of the first transmitting area and the central transverse lines do not coincide with each other.
2. The method of claim 1 , wherein the transmitting areas include a plurality of stepwise slits having a stepwise outline and having lengths and widths and arranged in their width direction.
3. The method of claim 2 , wherein the transmitting areas further include a plurality of rectangular slits arranged to form a column, and the plurality of stepwise slits are arranged to form another column.
4. The method of claim 3 , wherein the plurality of stepwise slits and the plurality of rectangular slits are arranged offset.
5. A method of manufacturing an electroluminescent display device including a plurality of switching thin film transistors, a plurality of driving thin film transistors, and a plurality of organic light emitting members, the method comprising:
depositing an amorphous silicon layer for the driving thin film transistors;
melting the amorphous silicon layer by illuminating a laser beam through a mask including a plurality of transmitting areas and a plurality of blocking areas; and
forming a crystallized silicon layer by crystallizing the melted amorphous silicon layer,
wherein a first outline of a first transmitting area of the transmitting areas has a stepwise shape and the first outline having the stepwise shape is formed as only one of an upper outline and a lower outline of the first transmitting area,
wherein grain boundaries of the crystallized silicon layer do not coincide with each other between the first outline of the first transmitting area and a second outline of the first transmitting area opposite the first outline,
wherein the gain boundaries form central transverse lines between the first outline of the first transmitting area and the second outline of the first transmitting area and the central transverse lines do not coincide with each other.