Boost capacitor circuit and charge pump
View Patent ↗A boost capacitor circuit is disclosed which includes a first nMOS transistor and a voltage doubler circuit including: a first pMOS transistor having a drain coupled to a working voltage, a source coupled to a first node and a gate coupled to a second node; a drive inverter having an input terminal for receiving a first signal; a second pMOS transistor having a gate coupled to an output terminal of the drive inverter, a source and a drain coupled to each other and further to the first node; a third pMOS transistor having a gate for receiving the first signal, a source coupled to the first node and a drain coupled to the second node; and a second nMOS transistor having a gate for receiving the first signal, a source coupled to a low voltage and a drain coupled to the second node.
1. A boost capacitor circuit, comprising a first nMOS transistor and a voltage doubler circuit, the first nMOS transistor having a gate for providing a boosted voltage, the voltage doubler circuit comprising:
a first pMOS transistor, having a drain coupled to a working voltage, a source coupled to a first node and a gate coupled to a second node;
a drive inverter, having an input terminal for receiving a first signal;
a second pMOS transistor, having a gate coupled to an output terminal of the drive inverter, a source and a drain coupled to each other and further to the first node;
a third pMOS transistor having a gate for receiving the first signal, a source coupled to the first node and a drain coupled to the second node; and
a second nMOS transistor, having a gate for receiving the first signal, a source coupled to a low voltage and a drain coupled to the second node,
wherein a source and a drain of the first nMOS transistor are coupled to each other and further to the second node for receiving a second signal from the second node.
2. The boost capacitor circuit according to claim 1 , wherein the first signal is valid when a voltage thereof is equal to the working voltage.
3. The boost capacitor circuit according to claim 1 , wherein the second signal is invalid when the first signal is valid, and the second signal is valid and has a voltage that is twice the working voltage when the first signal is invalid.
4. The boost capacitor circuit according to claim 1 , wherein the first nMOS transistor is a thick-gate-oxide nMOS transistor.
5. The boost capacitor circuit according to claim 4 , wherein the first nMOS transistor has a gate oxide layer with a thickness of 60-200 Å.
6. The boost capacitor circuit according to claim 1 , wherein the first pMOS transistor and the second pMOS transistor are both thin-gate-oxide pMOS transistors.
7. The boost capacitor circuit according to claim 6 , wherein both of the first pMOS transistor and the second pMOS transistor have a gate oxide layer with a thickness of smaller than 40 Å.
8. The boost capacitor circuit according to claim 1 , wherein the third pMOS transistor is a thick-gate-oxide pMOS transistor.
9. The boost capacitor circuit according to claim 8 , wherein the third pMOS transistor has a gate oxide layer with a thickness of 60-200 Å.
10. The boost capacitor circuit according to claim 1 , wherein the second nMOS transistor is a thick-gate-oxide nMOS transistor.
11. The boost capacitor circuit according to claim 10 , wherein the second nMOS transistor has a gate oxide layer with a thickness of 60-200 Å.
12. A charge pump, comprising n stages of boost capacitor circuits as defined in claim 1 , wherein the gates of the first nMOS transistors of the n stages of boost capacitor circuits are connected one after another, and wherein n is a positive integer greater than or equal to 2.
13. The charge pump according to claim 12 , wherein the gates of the first nMOS transistors of the n stages of boost capacitor circuits that are connected one after another are coupled to an output terminal of the charge pump for providing an output voltage to a memory cell.
14. The charge pump according to claim 13 , wherein a switching element is disposed between each adjacent two of the n stages of boost capacitor circuits and between a last one of the n stages of boost capacitor circuits and the output terminal.