Gate structure for semiconductor device

1. A method of forming a semiconductor device, the method comprising:

forming a source/drain region on a substrate;

forming spacers on the substrate;

forming an etch stop layer on the spacers and the source/drain region;

forming a gate structure between the spacers;

etching back the gate structure;

etching back, after the etching back of the gate structure, the spacers and the etch stop layer; and

forming a gate capping structure on the etched back gate structure, spacers, and etch stop layer.

2. The method of claim 1 , wherein the forming the gate capping structure comprises:

depositing an insulating material on the etched back gate structure, spacers, and etch stop layer; and

planarizing the insulating material.

3. The method of claim 1 , wherein the forming the gate capping structure comprises:

forming a first insulating layer on the etched back gate structure, spacers, and etch stop layer; and

forming a second insulating layer on the first insulating layer.

4. The method of claim 1 , wherein the forming the gate capping structure comprises:

depositing a first insulating material on the etched back gate structure, spacers, and etch stop layer;

etching back the first insulating layer;

depositing a second insulating material on the etched back insulating layer; and

planarizing the second insulating material.

5. The method of claim 1 , wherein the etching back the spacers and the etch back layer comprises:

a dry etch process; and

an oxide deposition process.

6. The method of claim 1 , wherein the etching back the spacers and the etch back layer comprises performing a dry etch process and an oxide deposition process in a cyclic manner repeated 1 to 10 times.

7. The method of claim 1 , further comprising:

forming an etch stop layer on the spacers;

etching back the etch stop layer such that a top surface of the etch stop layer is coplanar with a top surface of the first layer.

8. The method of claim 4 , wherein the etching back the first insulating layer comprises:

a dry etch process; and

an oxide deposition process.

9. The method of claim 4 , wherein the etching back the first insulating layer comprises performing a dry etch process and an oxide deposition process in a cyclic manner repeated 1 to 10 times.

10. The method of claim 4 , wherein the etching back the first insulating layer comprises performing a wet etch process using an etchant having phosphoric acid.

11. The method of claim 4 , wherein the etching back the first insulating layer comprises performing a dry etch process using a fluorine-based etchant.

12. A method of forming a semiconductor device, the method comprising:

forming a source/drain region on a substrate;

forming spacers on the substrate;

forming a gate structure between the spacers;

etching back the gate structure;

forming a first layer of a gate capping structure on the etched back gate structure;

etching back, after the etching back of the gate structure, the spacers; and

forming a second layer of the gate capping structure on the first layer and the etched back spacers.

13. The method of claim 12 , wherein the forming the first layer comprises:

depositing an insulating material on the etched back gate structure;

planarizing the insulating material; and

etching back the planarized insulating material.

14. The method of claim 12 , wherein the forming the first layer comprises:

depositing an insulating material on the etched back gate structure; and

etching back the insulating material by performing a dry etch process and an oxide deposition process in a cyclic manner repeated 1 to 10 times.

15. The method of claim 12 , wherein the forming the first layer comprises:

depositing an insulating material on the etched back gate structure; and

etching back the insulating material by performing a wet etch process using an etchant having phosphoric acid.

16. The method of claim 12 , wherein the forming the first layer comprises:

depositing an insulating material on the etched back gate structure; and

etching back the insulating material by performing a dry etch process using a fluorine-based etchant.

17. The method of claim 12 , wherein the forming the second layer comprises:

depositing an insulating material on the first layer and the etched back spacers; and

planarizing the insulating material.

18. A semiconductor device comprising:

a source/drain region on a substrate;

an interlayer dielectric (ILD) layer over the source/drain region;

a gate structure on the substrate;

spacers positioned on opposing sides of the gate structure;

an etch stop layer on sidewalls of the spacers; and

a gate capping structure positioned within the ILD layer and on the gate structure, the spacers, and the etch stop layer, wherein a width of the gate capping structure is larger than a gate length of the gate structure.

19. The semiconductor device of claim 18 , wherein the gate capping structure comprises:

a first insulating layer positioned on the gate structure, the spacers, and the etch stop layer; and

a second insulating layer positioned on the first insulating layer, wherein:

a width of the first insulating layer is equal to a width of the second insulating layer; and

the widths of the first and second insulating layers are greater than the gate length of the gate structure.

20. The semiconductor device of claim 18 , wherein the gate capping structure comprises:

a first insulating layer positioned between the spacers and on the gate structure; and

a second insulating layer positioned on the first insulating layer, the spacers, and the etch stop layer, wherein:

a width of the first insulating layer is smaller than a width of the second insulating layer; and

the width of the first insulating layer is equal to the gate length of the gate structure.