Bitflip security attack protection
A memory area is protected from rowhammer attacks by placing an extra sacrificial row at the top and the bottom of the memory addresses defining the area to be protected. The sacrificial rows of memory are written with a known bit pattern that may be read periodically to detect any rowhammer attacks that may be in progress.
1. A memory device comprising:
an array of memory cells arranged in rows and columns;
a plurality of word lines each coupled to memory cells of a respective one of the rows;
a plurality of bit lines each coupled to memory cells of a respective one of the columns;
wherein the array includes:
a contiguous segment of protected memory cells, the contiguous segment of protected memory cells including a plurality of the rows;
a first sacrificial row outside of the contiguous segment and immediately adjacent to a first row of the contiguous segment; and
a second sacrificial row outside of the contiguous segment and immediately adjacent to a second row of the contiguous segment that is different from the first row.
2. The memory device of claim 1 , comprising a memory controller to generate a memory address in response to received requests to access the memory cells of the array.
3. The memory device of claim 2 , comprising a row address decoder to select one or more word lines of the array in response to the generated memory address.
4. The memory device of claim 2 , comprising a column address decoder to select one or more bit lines of the array in response to the generated memory address.
5. The memory device of claim 2 , wherein the first and second sacrificial rows are operable to store a predetermined known bit pattern.
6. The memory device of claim 5 , wherein the memory controller is operable to periodically read contents of the first and second sacrificial rows to determine whether the contents of the first and second sacrificial rows has changed from the predetermined known bit pattern.
7. The memory device of claim 6 , wherein the memory controller is operable to indicate a presence of a rowhammer attack upon determining that the contents of the first and second sacrificial rows has changed from the predetermined known bit pattern.
8. The memory device of claim 1 , wherein:
the first sacrificial row has an address that is contiguous with an address of the first row of the contiguous segment of protected memory cells; and
the second sacrificial row has an address that is contiguous with an address of the second row of the contiguous segment of protected memory cells.
9. The memory device of claim 8 , wherein the contiguous segment of protected memory cells, the first sacrificial row, and the second sacrificial row constitute an entirety of the array.
10. The memory device of claim 8 , wherein:
the array includes unprotected memory cells outside of the contiguous segment of protected memory cells; and
at least one of the first and second sacrificial rows is also immediately adjacent to a row of the unprotected memory cells.
11. The memory device of claim 10 , wherein only one of the first and second sacrificial rows is also immediately adjacent to a row of the unprotected memory cells.
12. An electronic system comprising
a processor;
a memory storing instructions for execution by the processor, wherein the memory includes:
an array of memory cells arranged in rows and columns;
a plurality of word lines each coupled to memory cells of a respective one of the rows;
a plurality of bit lines each coupled to memory cells of a respective one of the columns;
a memory controller to generate a memory address in response to the processor issuing an access request to access the memory cells of the array, the access request being issued in response to the processor executing the instructions;
a row address decoder to select one or more word lines of the array in response to the generated memory address;
a column address decoder to select one or more bit lines of the array in response to the generated memory address;
wherein the array includes:
a contiguous segment of protected memory cells, the contiguous segment of protected memory cells including a plurality of the rows;
a first sacrificial row outside of the contiguous segment and immediately adjacent to a first row of the contiguous segment; and
a second sacrificial row outside of the contiguous segment and immediately adjacent to a second row of the contiguous segment that is different from the first row.
13. The electronic system of claim 12 , wherein the first and second sacrificial rows are operable to store a predetermined known bit pattern.
14. The electronic system of claim 13 , wherein the memory controller is operable to periodically read contents of the first and second sacrificial rows to determine whether the contents of the first and second sacrificial rows has changed from the predetermined known bit pattern.
15. The electronic system of claim 14 , wherein the memory controller is operable to indicate a presence of a rowhammer attack upon determining that the contents of the first and second sacrificial rows has changed from the predetermined known bit pattern.
16. The electronic system of claim 12 , wherein:
the first sacrificial row has an address that is contiguous with an address of the first row of the contiguous segment of protected memory cells; and
the second sacrificial row has an address that is contiguous with an address of the second row of the contiguous segment of protected memory cells.
17. The electronic system of claim 16 , wherein the contiguous segment of protected memory cells, the first sacrificial row, and the second sacrificial row constitute an entirety of the array.
18. The electronic system of claim 16 , wherein:
the array includes unprotected memory cells outside of the contiguous segment of protected memory cells; and
at least one of the first and second sacrificial rows is also immediately adjacent to a row of the unprotected memory cells.
19. The electronic system of claim 18 , wherein only one of the first and second sacrificial rows is also immediately adjacent to a row of the unprotected memory cells.