IP Library Granted Patent US 10,198,540
Granted Patent B1
US 10,198,540 · App. 14/039,116 · Granted Feb 5, 2019

System and method for profiling during an electronic design simulation

Inventor: Daniel Asher Cohen (Los Gatos, CA)
Assignee: Cadence Design Systems, Inc.
G06F17/5031G06F11/3636
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Quick Facts
Patent No.
US 10,198,540
App. No.
14/039,116
Granted
Feb 5, 2019
Kind
B1
Abstract

The present disclosure relates to a computer-implemented method for electronic design simulation using a profiler. The method may include simulating, using a computing device, an electronic design associated with a programming language. The method may further include recording a first time corresponding to a first user-defined point in the simulation. The method may also include recording a second time corresponding to a second user-defined point in the simulation. The method may further include determining a difference in time between the first and second times and displaying a visualization including at least one of the first time, the second time, a value of a variable at the first time, a value of the variable at a second time, and the difference in time.

Claims (28)

1. A computer-implemented method for electronic design simulation using a profiler comprising:

simulating, using a computing device, an electronic design associated with a programming language;

recording a first time corresponding to a first user-defined point in a simulation;

recording a second time corresponding to a second user-defined point in the simulation;

determining a difference in time between the first and second times; and

displaying a non-waveform, numerical-based visualization including the first time, the second time, a value of a variable at the first time, a value of the variable at the second time, and the difference in time, wherein the non-waveform based visualization includes a tree display having one or more user-selectable sub-portions and wherein each of the one or more user-selectable sub-portions is configured to display a percentage of resources consumed during the simulation;

accessing the electronic design using a direct programming interface (DPI); and

using the electronic design, at least in part, to fabricate an integrated circuit or printed circuit board.

2. The computer-implemented method of claim 1 , wherein the programming language is one of C, C ++ , Verilog, and SystemVerilog.

3. The computer-implemented method of claim 1 , wherein the first user-defined point is associated with a breakpoint in a graphical debugging environment.

4. The computer-implemented method of claim 1 , wherein the profiler is associated with a base class library.

5. The computer-implemented method of claim 1 , wherein the first user-defined point in the simulation corresponds to a starting point in the simulation and the second user-defined point corresponds to an ending point in the simulation.

6. The computer-implemented method of claim 1 , further comprising:

identifying the value of the variable at the first time.

7. A non-transitory computer-readable storage medium for electronic design simulation using a profiler, the computer-readable storage medium having stored thereon instructions that when executed by a machine result in the following operations:

simulating, using a computing device, an electronic design associated with a programming language;

recording a first time corresponding to a first user-defined point in a simulation;

recording a second time corresponding to a second user-defined point in the simulation;

determining a difference in time between the first and second times;

displaying a non-waveform, numerical-based visualization including the first time, the second time, a value of a variable at the first time, a value of the variable at the second time, and the difference in time, wherein the non-waveform based visualization includes a tree display having one or more user-selectable sub-portions and wherein each of the one or more user-selectable sub-portions is configured to display a percentage of resources consumed during the simulation;

accessing the electronic design using a direct programming interface (DPI); and

using the electronic design, at least in part, to fabricate an integrated circuit or printed circuit board.

8. The computer-readable storage medium of claim 7 , wherein the programming language is one of C, C ++ , Verilog, and SystemVerilog.

9. The computer-readable storage medium of claim 7 , wherein the first user-defined point is associated with a breakpoint in a graphical debugging environment.

10. The computer-readable storage medium of claim 7 , wherein the profiler is associated with a base class library.

11. The computer-readable storage medium of claim 7 , wherein the first user-defined point in the simulation corresponds to a starting point in the simulation and the second user-defined point corresponds to an ending point in the simulation.

12. The computer-readable storage medium of claim 7 , further comprising:

identifying the value of the variable at the first time.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 27, 2013
From: COHEN, DANIEL ASHER
To: CADENCE DESIGN SYSTEMS, INC.
Reel/Frame 031297/0039 →
Cited By (1)
US 12,488,161