Quadrature oscillation circuit and CDR circuit

1. A quadrature oscillation circuit comprising

a plurality of adjacent quadrature oscillators, wherein

a first quadrature oscillator in the quadrature oscillators includes

a first I-phase inductor,

a first Q-phase inductor, and

a first drive circuit that generates a first I-phase current passing through the first I-phase inductor and a first Q-phase current passing through the first Q-phase inductor such that phases of a first I-phase differential signal output from both sides of the first I-phase inductor and phases of a first Q-phase differential signal output from both sides of the first Q-phase inductor are different from each other,

a second quadrature oscillator in the quadrature oscillators includes

a second I-phase inductor,

a second Q-phase inductor, and

a second drive circuit that generates a second I-phase current passing through the second I-phase inductor and a second Q-phase current passing through the second Q-phase inductor such that phases of a second I-phase differential signal output from both sides of the second I-phase inductor and phases of a second Q-phase differential signal output from both sides of the second Q-phase inductor are different from each other, and

the second drive circuit generates the second Q-phase current whose phase is inversed with respect to the phase of the first Q-phase current when the first I-phase current and the second I-phase current are in phase, and generates the second I-phase current whose phase is inversed with respect to the phase of the first I-phase current when the first Q-phase current and the second Q-phase current are in phase.

2. The quadrature oscillation circuit according to claim 1 , wherein

the first drive circuit delays the phase of the first Q-phase current with respect to the phase of the first I-phase current such that the phases of the first Q-phase differential signal are delayed with respect to the phases of the first I-phase differential signal, and

the second drive circuit advances the phase of the second Q-phase current with respect to the phase of the second I-phase current such that the phases of the second Q-phase differential signal are advanced with respect to the phases of the second I-phase differential signal.

3. The quadrature oscillation circuit according to claim 1 , wherein the first I-phase inductor and the second I-phase inductor are symmetric with respect to a line and the first Q-phase inductor and the second Q-phase inductor are symmetric with respect to a line.

4. The quadrature oscillation circuit according to claim 1 , wherein the first I-phase inductor and the second I-phase inductor are disposed such that the axis directions are parallel to each other and the first Q-phase inductor and the second Q-phase inductor are disposed such that the axis directions are parallel to each other.

5. A clock and data recovery (CDR) circuit comprising:

a plurality of adjacent quadrature oscillators; and

a plurality of CDR parts in the respective quadrature oscillators, wherein

each of the CDR parts recovers, from a data signal including superimposed clocks, the clocks and data in accordance with a four-phase signal output from a corresponding quadrature oscillator,

a first quadrature oscillator in the quadrature oscillators includes a first I-phase inductor, a first Q-phase inductor, and a first drive circuit that generates a first I-phase current passing through the first I-phase inductor and a first Q-phase current passing through the first Q-phase inductor such that phases of a first I-phase differential signal output from both sides of the first I-phase inductor and phases of a first Q-phase differential signal output from both sides of the first Q-phase inductor are different from each other,

a second quadrature oscillator in the quadrature oscillators includes a second I-phase inductor, a second Q-phase inductor, and a second drive circuit that generates a second I-phase current passing through the second I-phase inductor and a second Q-phase current passing through the second Q-phase inductor such that phases of a second I-phase differential signal output from both sides of the second I-phase inductor and phases of a second Q-phase differential signal output from both sides of the second Q-phase inductor are different from each other, and

the second drive circuit generates the second Q-phase current whose phase is inversed with respect to the phase of the first Q-phase current when the first I-phase current and the second I-phase current are in phase, and generates the second I-phase current whose phase is inversed with respect to the phase of the first I-phase current when the first Q-phase current and the second Q-phase current are in phase.

6. The CDR circuit according to claim 5 , wherein

the first drive circuit delays the phase of the first Q-phase current with respect to the phase of the first I-phase current such that the phases of the first Q-phase differential signal are delayed with respect to the phases of the first I-phase differential signal, and

the second drive circuit advances the phase of the second Q-phase current with respect to the phase of the second I-phase current such that the phases of the second Q-phase differential signal are advanced with respect to the phases of the second I-phase differential signal.

7. The CDR circuit according to claim 5 , wherein the first I-phase inductor and the second I-phase inductor are symmetric with respect to a line and the first Q-phase inductor and the second Q-phase inductor are symmetric with respect to a line.

8. The CDR circuit according to claim 5 , wherein the first I-phase inductor and the second I-phase inductor are disposed such that the axis directions are parallel to each other and the first Q-phase inductor and the second Q-phase inductor are disposed such that the axis directions are parallel to each other.