Multifunction three quarter bridge
View Patent ↗Some apparatus and associated methods relate to a buck-derived switched mode power supply with three-quarter bridge (TQB) formed with a bypass switch in parallel with an inductor. In an illustrative example, the bypass switch may be configured to, in response to a decrease in average load demand, operate in a first mode to turn on the bypass switch to selectively circulate inductor current through the bypass switch while a high-side switch and a low-side switch are off. In a second mode, the bypass switch may be turned off to circulate the inductor current through, for example, an output capacitor and the low-side switch. In some implementations of the TQB, the bypass switch may be operated, for example, to selectively transfer a controlled amount of energy stored in the inductor to the output capacitor in response to a decrease in average load demand.
1. A buck-derived switched mode power supply apparatus with a three-quarter bridge (TQB) configuration, the apparatus comprising:
a main switch operative to selectively connect a first terminal of an input voltage source to an intermediate switch node;
an inductor having a first terminal coupled to the intermediate switch node and a second terminal coupled to an output node adapted to communicate energy to a load;
a freewheeling rectifier coupled to conduct current from a second terminal of the input voltage source to the intermediate switch node; and,
a bypass switch arranged in parallel with the inductor and formed of a first controllable semiconductor switch and a second controllable semiconductor switch connected in anti-series and configured to modulate conductivity between the intermediate switch node and the output node in response to a bypass switch control signal.
2. The apparatus of claim 1 , wherein the bypass switch is further arranged such that when only the first controllable semiconductor switch is turned on, current can pass through the bypass switch in only a first direction, and when only the second controllable semiconductor switch is turned on, current can pass through the bypass switch in only a second direction, and when both the first and the second controllable semiconductor switches are turned on, current can pass through the bypass switch in either the first direction or the second direction.
3. The apparatus of claim 1 , wherein the first and the second controllable semiconductor switches are series-connected in a common drain configuration.
4. The apparatus of claim 1 , wherein the first and the second controllable semiconductor switches are series-connected in a common source configuration.
5. The apparatus of claim 1 , further comprising an integrated circuit package formed as a unitary body, wherein at least the bypass switch, the main switch, and the freewheeling rectifier are disposed within the integrated circuit package.
6. The apparatus of claim 1 , further comprising an integrated circuit package formed as a unitary body, wherein at least the bypass switch and the inductor are disposed within the integrated circuit package.
7. The apparatus of claim 1 , further comprising an integrated circuit package formed as a unitary body having only three terminals for making connection to the bypass switch, wherein at least the bypass switch and a gate driver circuit are disposed within the integrated circuit package, and wherein the three terminals include an input terminal operatively connected to the intermediate switch node, an output terminal operatively connected to the output node, and a control input terminal operatively connected to the gate driver circuit and to receive the bypass switch control signal.
8. The apparatus of claim 1 , wherein the bypass switch comprises at least one P-channel MOSFET.
9. The apparatus of claim 1 , wherein the bypass switch comprises at least one N-channel MOSFET.
10. The apparatus of claim 1 , further comprising a multimode driver circuit operatively coupled to the bypass switch and configured to generate the bypass switch control signal to operate the bypass switch in a plurality of different modes in response to load conditions.
11. The apparatus of claim 10 , wherein one of the plurality of different modes comprises generating the bypass switch control signal to cause at least one of the first controllable semiconductor switch and the second controllable semiconductor switch to operate in a full on mode characterized by a substantially minimum channel resistance state.
12. The apparatus of claim 10 , wherein one of the plurality of different modes comprises generating the bypass switch control signal to cause at least one of the first controllable semiconductor switch and the second controllable semiconductor switch to operate in a controlled resistance mode characterized by regulating to a predetermined ratio of a voltage across the at least one switch to a current through the at least one switch.
13. The apparatus of claim 10 , wherein one of the plurality of different modes comprises generating the bypass switch control signal to cause at least one of the first controllable semiconductor switch and the second controllable semiconductor switch to operate in a controlled current mode characterized by regulating a predetermined current through the at least one switch.
14. The apparatus of claim 10 , wherein one of the plurality of different modes comprises generating the bypass switch control signal to cause at least one of the first controllable semiconductor switch and the second controllable semiconductor switch to operate in a controlled voltage mode characterized by regulating a predetermined voltage between a predetermined node of the bypass switch and a predetermined reference node.
15. The apparatus of claim 14 , wherein the predetermined node of the bypass switch comprises the output node and the predetermined reference node comprises a circuit ground reference for the load.
16. The apparatus of claim 1 , further comprising a gate drive circuit to interface a first control signal associated with the bypass switch control signal to a first control terminal of the first controllable semiconductor switch and a second control signal associated with the bypass switch control signal to a second control terminal of the second controllable semiconductor switch.
17. The apparatus of claim 1 , further comprising a bypass switch controller operative to generate the bypass switch control signal to operate the bypass switch to selectively transfer a controlled amount of energy stored in the inductor to the output node by performing operations, the operations comprising:
in a first mode, operate the bypass switch to selectively cause the inductor current to circulate through the bypass switch; and,
in a second mode, operate the bypass switch to cause the inductor current to circulate via the output terminal to the load and return through the freewheeling rectifier.
18. The apparatus of claim 17 , wherein the bypass switch controller is configured to iteratively perform further operations to:
enter the second mode in response to a voltage at the output terminal reaching a predetermined lower threshold; and,
enter the first mode in response to the voltage at the output terminal reaching a predetermined upper threshold.
19. The apparatus of claim 17 , wherein the bypass switch controller is configured to iteratively perform further operations to:
while in the first mode, and upon a voltage at the output terminal falling below a predetermined lower threshold, enter the second mode; and
upon reaching a predetermined duration of time in the second mode, enter the first mode.
20. The apparatus of claim 17 , wherein the bypass switch controller is configured to iteratively perform further operations to:
enter the first mode in response to a voltage at the output terminal reaching a predetermined upper threshold;
if the current in the inductor exceeds a predetermined first current threshold when the voltage at the output terminal reaches a predetermined lower threshold:
a) control the main switch to remain in an off state until the inductor current falls below a predetermined second current threshold;
b) enter the second mode in response to the voltage at the output terminal reaching the predetermined lower threshold; and,
c) enter the first mode in response to the voltage at the output terminal reaching the predetermined upper threshold.