Charge pump circuits for clock and data recovery
The present invention is directed to electrical circuits. More specifically, embodiments of the present invention provide a charge pump, which can be utilized as a part of a clock data recovery device. Early and late signals are used as differential switching voltage signals in the charge pump. The first switch and a second switch are used for controlling the direction of the current flowing into the loop filter. Input differential voltages to the switches are being generated with an opamp negative feedback loop. The output voltage of the first switch and the second switch is used in conjunction with a resistor to generate a charge pump current. There are other embodiments as well.
1. A clock data recovery device comprising:
a data sampler for performing data sampling on received data signals and generating a data clock signal, the data sampler being configured to adjust the data clock signal using a loop filter voltage;
an edge sampler for performing sampling on the received data signals during the transitions and generating an edge clock signal;
a phase detector configured to generate an early and a late signal using the data clock signal and the edge clock signal;
a charge pump module comprising a first switch and a second switch and an output resistor, the charge pump module being configured to provide a pair of differential voltages, the pair of differential voltages including a first voltage based on the late signal and coupled to the first switch, the pair of differential voltages including a second voltage based on the early signal and coupled to the second switch, the output resistors being configured to output a charge pump current based on the pair of differential voltages, a first output of the first switch being directly coupled to a second output of the second switch; and
a loop filter being configured to generate the loop filter voltage based on the charge pump current.
2. The device of claim 1 wherein the charge pump further comprises a third switch for providing equalization between the first switch and the second switch.
3. The device of claim 1 wherein the edge sampler is configured to adjust the edge clock signal using at least the loop filter voltage.
4. The device of claim 1 wherein the phase detector comprises a bang-bang phase detector.
5. The device of claim 1 wherein the charge pump current has a magnitude of less than 40 uA.
6. The device of claim 1 wherein the first switch is coupled to a first capacitor, and the second switch is coupled to a second capacitor, the first capacitor and the second capacitor are a matched pair.
7. The device of claim 1 wherein the first switch is coupled to a first resistor, and the second switch is coupled to a second resistor, the first resistor and the second resistor are a matched pair.
8. The device of claim 1 wherein the charge pump further comprises an operational amplifier.
9. The device of claim 1 wherein the charge pump current is positive when the first switch is closed.
10. The device of claim 1 wherein the charge pump current is negative when the first switch is closed.