Transistor substrate and display device
View Patent ↗In a transistor substrate of a display device, a plurality of signal lines to which any one of drive signals of a gate signal and a video signal is supplied include a plurality of first signal lines to which the drive signal is supplied. The first signal line is connected to a driving driver, and is formed in an edge region positioned between an end portion of a substrate and a pixel region and in the pixel region. The first signal line is formed to pass through a first wiring formed in a first layer from a second wiring formed in a second layer in the edge region.
1. A transistor substrate comprising:
a substrate having a pixel region and a peripheral region which is positioned between an edge of the substrate and the pixel region;
a plurality of pixels in the pixel region;
a driving circuit configured to output a video signal in the peripheral region; a first wiring layer includes a plurality of lines;
a second wiring layer;
a first insulating film provided between the first wiring layer and the second wiring layer; and
a plurality of input connections electrically connecting the driving circuit to signal paths in the peripheral region, wherein
signal paths include a first signal path and a second signal path adjacent to the first signal path, and electrically connect the plurality of input connections to the plurality of pixels,
the plurality of input connections is arranged along a first direction, the first and the second signal paths include conversion portions,
the conversion portions are located between slanted regions in which the signal paths slant relative to the first direction,
in the peripheral region, the first signal path and the second signal path traverse the first wiring layer and the second wiring layer, and
in one of the slanted regions, a distance between the first signal path and the second signal path is narrower than a line pitch of the first wiring layer.
2. The transistor substrate according to claim 1 , wherein
a material of the first wiring layer is different from a material of the second wiring layer, and
a specific resistance of the material of the second wiring layer is lower than a specific resistance of the material of the first wiring layer.
3. The transistor substrate according to claim 1 , wherein a line width of the first wiring layer is greater than a line width of the second wiring layer.
4. The transistor substrate according to claim 1 further comprising: a third wiring layer formed on the second wiring layer, wherein
the first signal path and the second signal path traverse, in the peripheral region, the first wiring layer, the second wiring layer, and the third wiring layer.
5. The transistor substrate according to claim 4 , wherein
a line width of the third wiring layer is larger than a line width of the second wiring layer, and
the line width of the third wiring layer is smaller than a line width of the first wiring layer.
6. The transistor substrate according to claim 1 , wherein a thickness of the second wiring layer is greater than a thickness of the first wiring layer.
7. The transistor substrate according to claim 1 , wherein a part of the first wiring layer overlaps a part of the second wiring layer.
8. The transistor substrate according to claim 1 , wherein, the conversion portions include a first conversion portion and a second conversion portion adjacent to the first conversion portion, and
the first signal path traverses from the first wiring layer to the second wiring layer through the first conversion portion, and the second signal path traverses from the second wiring layer to the first wiring layer through the second conversion portion.
9. The transistor substrate according to claim 8 , wherein a part of the first wiring layer directly contacts with a part of the second wiring layer in the conversion portions.
10. The transistor substrate according to claim 1 , wherein the driving circuit is a semiconductor chip.
11. The transistor substrate according to claim 1 , wherein an intersection portion is provided in the peripheral region, the intersection portion causing the plurality of signal paths to cross each other such that, relative positions within an array order of two or more of the plurality of signal paths are changed.
12. The transistor substrate according to claim 1 , wherein, a part of the first signal path overlaps a part of the second signal path.
13. The transistor substrate according to claim 12 , wherein, in a region where the part of the first signal path overlaps the part of the second signal path, the first signal path extends in a same direction as the second signal path.
14. The transistor substrate according to claim 1 , wherein the plurality of signal paths slants relative to a direction from the plurality of input connections to the pixel region in the slanted regions.