Fabric management system and method
A PCIe fabric is configured to couple a plurality of elements. The PCIe fabric includes a plurality of PCIe subfabrics. A primary master central processing system is configured to couple the plurality of PCIe subfabrics and includes a primary master central processing unit.
1. A Peripheral Component Interconnect Express (PCIe) fabric configured to couple a plurality of elements, the PCIe fabric comprising:
a plurality of PCIe subfabrics each comprising a managing central processing unit; and
a primary master central processing system configured to couple the plurality of PCIe subfabrics and including a primary master central processing unit, wherein the primary master central processing system is configured to:
determine the topology of the plurality of PCIe subfabrics, wherein determining the topology of the plurality of PCIe subfabrics includes: determining a number of managing central processing units included within the PCIe fabric, and determining the types of elements coupled with the PCIe fabric,
determine the topology of the entire PCIe fabric based upon, at least in part, the topology of the plurality of PCIe subfabrics, and share the topology of the entire PCIe fabric with each of the plurality of PCI subfabrics.
2. The PCIe fabric of claim 1 wherein the primary master central processing system includes:
a primary fan-out switch configured to electrically couple the primary master central processing unit and the plurality of PCIe subfabrics.
3. The PCIe fabric of claim 1 further comprising:
a secondary master central processing system configured to couple the plurality of PCIe subfabrics and including a secondary master central processing unit.
4. The PCIe fabric of claim 3 wherein the secondary master central processing system includes:
a secondary fan-out switch configured to electrically couple the secondary master central processing unit and the plurality of PCIe subfabrics.
5. The PCIe fabric of claim 1 wherein each of the plurality of PCIe subfabrics includes further comprise:
a managing central processing unit, and a PCIe fabric switch.
6. The PCIe fabric of claim 5 further comprising:
one or more communication paths configured to allow communication between the PCIe fabric switch included within each of the plurality of PCIe subfabrics.
7. The PCIe fabric of claim 1 wherein the plurality of elements include components of a data storage system.
8. The PCIe fabric of claim 1 wherein the plurality of elements includes one or more host elements.
9. The PCIe fabric of claim 8 wherein the one or more host elements include one or more compute modules.
10. The PCIe fabric of claim 1 wherein the plurality of elements includes one or more endpoint elements.
11. The PCIe fabric of claim 10 wherein the one or more endpoint elements include one or more of:
one or more host bus adaptors;
Serial Attached Small Computer System Interface (SAS) controllers;
SAS hard disk drives;
fiber channel adapters;
Ethernet adapters;
PCIe flash memory devices;
one or more InfiniBand (IB) adapters;
one or more Redundant Array of Independent Disks (RAID) adapters;
one or more network adapters; and
one or more general purpose graphics processing units.
12. A Peripheral Component Interconnect Express (PCIe) fabric configured to couple a plurality of elements, the PCIe fabric comprising:
a plurality of PCIe subfabrics; and
a primary master central processing system configured to couple the plurality of PCIe subfabrics and including a primary master central processing unit and a primary fan-out switch configured to electrically couple the primary master central processing unit and the plurality of PCIe subfabrics;
wherein each of the plurality of PCIe subfabrics includes: a managing central processing unit, and a PCIe fabric switch; and
wherein the primary master central processing system is configured to: determine the topology of the plurality of PCIe subfabrics, wherein determining the topology of the plurality of PCIe subfabrics includes:
determining a number of managing central processing units included within the PCIe fabric, and
determining the types of elements coupled with the PCIe fabric,
determine the topology of the entire PCIe fabric based upon, at least in part, the topology of the plurality of PCIe subfabrics, and share the topology of the entire PCIe fabric with each managing central processing unit of the plurality of PCI subfabrics.
13. The PCIe fabric of claim 12 further comprising:
one or more communication paths configured to allow communication between the PCIe fabric switch included within each of the plurality of PCIe subfabrics.
14. The PCIe fabric of claim 12 further comprising:
a secondary master central processing system configured to couple the plurality of PCIe subfabrics and including a secondary master central processing unit.
15. The PCIe fabric of claim 14 wherein the secondary master central processing system includes:
a secondary fan-out switch configured to electrically couple the secondary master central processing unit and the plurality of PCIe subfabrics.
16. A Peripheral Component Interconnect Express (PCIe) fabric configured to couple a plurality of elements, the PCIe fabric comprising:
a plurality of PCIe subfabrics;
a primary master central processing system configured to couple the plurality of PCIe subfabrics and including a primary master central processing unit and a primary fan-out switch configured to electrically couple the primary master central processing unit and the plurality of PCIe subfabrics, wherein the primary master central processing system is configured to: determine the topology of the plurality of PCIe subfabrics, wherein determining the topology of the plurality of PCIe subfabrics includes: determining a number of managing central processing units included within the PCIe fabric, and determining the types of elements coupled with the PCIe fabric,
determine the topology of the entire PCIe fabric based upon, at least in part, the topology of the plurality of PCIe subfabrics, and share the topology of the entire PCIe fabric with each of the plurality of PCI subfabrics;
a secondary master central processing system configured to couple the plurality of PCIe subfabrics and including a secondary master central processing unit and a secondary fan-out switch configured to electrically couple the secondary master central processing unit and the plurality of PCIe subfabrics; and
one or more communication paths configured to allow communication between the PCIe fabric switch included within each of the plurality of PCIe subfabrics.
17. The PCIe fabric of claim 16 wherein the plurality of elements includes one or more host elements.
18. The PCIe fabric of claim 16 wherein the plurality of elements includes one or more endpoint elements.