Method and system for a compiler and decompiler

1. A system comprising:

one or more computer processors;

one or more computer memories;

one or more instructions incorporated into the computer memories, the one or more instructions configuring the one or more computer processors to perform operations for optimizing computer code, the operations comprising:

receiving a block of mixed intermediate representation (MIR) code;

for each instruction in the block of MIR code, in reverse order, generating a partially-decompiled block of computer code, the generating of the partially-decompiled block of computer code including computing a native expression vector for the instruction and repeating a set of pattern-matching operations until no transformations occur, the set of pattern-matching operations including matching all patterns involving the instruction in the block of MIR code, performing transformations based on the matching of all of the patterns in the block of the MIR code recomputing the expression vector after each of the transformations,

for each instruction in the partially-decompiled block of MIR code, in order, computing an additional native expression vector for the instruction in the partially-decompiled block of MIR code and performing an additional set of pattern-matching operations until no additional transformations occur, the additional set of pattern-matching operations including matching all additional patterns involving the instruction in the partially-decompiled block of computer code, and recomputing the expression vector after each of the additional transformations;

generating a fully-decompiled block of computer code from the generated partially-decompiled block of computer code, the fully-decompiled block of computer code having a semantic level that is raised; and

providing the fully-decompiled block of computer code for deployment on an architecture, the deployment including lowering the semantic of the computer code to a level that corresponds to a central processing unit (CPU) or graphical processing unit (GPU) supported by the architecture.

2. The system of claim 1 , wherein the MIR code is created by creating static single assignment form for a computer source code, simulating multiple assignments for named variables within the computer source code, creating a hash-map and populating the hash-map with the last definition of every named variable.

3. The system of claim 2 , wherein the generating of the fully-decompiled block of computer code further includes, based on no transformations occurring, running a common subexpression elimination pass.

4. The system of claim 2 , wherein the generating of the fully-decompiled block of computer code further includes, based on no transformations occurring, running a vectorization pass.

5. The system of claim 1 , wherein the expression vector includes a set of bits for source fields and an additional set of bits for an opcode and wherein the matching of all patterns involving the instruction in the block of MIR code is performed on the bits corresponding to the expression vector.

6. The system of claim 1 , wherein the semantic level corresponds to a higher native semantic level in which function calls are replaced with high-level native opcodes.

7. The system of claim 6 , wherein the high-level native opcodes allow use of mathematical identities to optimize the generating of the fully-decompiled block.

8. A computer-implemented method comprising:

performing operations for optimizing computer code, the operations comprising:

receiving a block of mixed intermediate representation (MIR) code;

for each instruction in the block of MIR code, in reverse order, generating a partially-decompiled block of computer code, the generating of the partially-decompiled block of computer code including computing a native expression vector for the instruction and repeating a set of pattern-matching operations until no transformations occur, the set of pattern-matching operations including matching all patterns involving the instruction in the block of MIR code, performing transformations based on the matching of all of the patterns in the block of the MIR code recomputing the expression vector after each of the transformations,

for each instruction in the partially-decompiled block of MIR code, in order, computing an additional native expression vector for the instruction in the partially-decompiled block of MIR code and performing an additional set of pattern-matching operations until no additional transformations occur, the additional set of pattern-matching operations including matching all additional patterns involving the instruction in the partially-decompiled block of computer code, and recomputing the expression vector after each of the additional transformations;

generating a fully-decompiled block of computer code from the generated partially-decompiled block of computer code, the fully-decompiled block of computer code having a semantic level that is raised; and

providing the fully-decompiled block of computer code for deployment on an architecture, the deployment including lowering the semantic of the computer code to a level that corresponds to a central processing unit (CPU) or graphical processing unit (GPU) supported by the architecture.

9. The computer-implemented method of claim 8 , wherein the MIR code is created by creating static single assignment form for a computer source code, simulating multiple assignments for named variables within the computer source code, creating a hash-map, and populating the hash-map with the last definition of every named variable.

10. The computer-implemented method of claim 8 , wherein the generating of the fully-decompiled block of computer code further includes, based on no transformations occurring, running a common subexpression elimination pass.

11. The computer-implemented method of claim 8 , wherein the generating of the fully-decompiled block of computer code further includes, based on no transformations occurring, running a vectorization pass.

12. The computer-implemented method of claim 8 , wherein the expression vector includes a set of bits for source fields and an additional set of bits for an opcode and wherein the matching of all patterns involving the instruction in the block of MIR code is performed on the bits corresponding to the expression vector.

13. The computer-implemented method of claim 8 , wherein the semantic level corresponds to a higher native semantic level in which function calls are replaced with high-level native opcodes.

14. The computer-implemented method of claim 13 , wherein the high-level native opcodes allow use of mathematical identities to optimize the generating of the fully-decompiled block.

15. A non-transitory computer-readable medium comprising a set of instructions, the set of instructions causing one or more computer processors to perform operations for optimizing computer code, the operations comprising:

receiving a block of mixed intermediate representation (MIR) code;

for each instruction in the block of MIR code, in reverse order, generating a partially-decompiled block of computer code, the generating of the partially-decompiled block of computer code including computing a native expression vector for the instruction and repeating a set of pattern-matching operations until no transformations occur, the set of pattern-matching operations including matching all patterns involving the instruction in the block of MIR code, performing transformations based on the matching of all of the patterns in the block of the MIR code recomputing the expression vector after each of the transformations,

for each instruction in the partially-decompiled block of MIR code, in order, computing an additional native expression vector for the instruction in the partially-decompiled block of MIR code and performing an additional set of pattern-matching operations until no additional transformations occur, the additional set of pattern-matching operations including matching all additional patterns involving the instruction in the partially-decompiled block of computer code, and recomputing the expression vector after each of the additional transformations;

generating a fully-decompiled block of computer code from the generated partially-decompiled block of computer code, the fully-decompiled block of computer code having a semantic level that is raised; and

providing the fully-decompiled block of computer code for deployment on an architecture, the deployment including lowering the semantic of the computer code to a level that corresponds to a central processing unit (CPU) or graphical processing unit (GPU) supported by the architecture.

16. The non-transitory computer-readable medium of claim 15 , wherein the MIR code is created by creating static single assignment form for a computer source code, simulating multiple assignments for named variables within the computer source code, creating a hash-map, and populating the hash-map with the last definition of every named variable.

17. The non-transitory computer-readable medium of claim 15 , wherein the generating of the fully-decompiled block of computer code further includes, based on no transformations occurring, running a common subexpression elimination pass.

18. The non-transitory computer-readable medium of claim 15 , wherein the generating of the fully-decompiled block of computer code further includes, based on no transformations occurring, running a vectorization pass.

19. The non-transitory computer-readable medium of claim 15 , wherein the expression vector includes a set of bits for source fields and an additional set of bits for an opcode and wherein the matching of all patterns involving the instruction in the block of MIR code is performed on the bits corresponding to the expression vector.

20. The non-transitory computer-readable medium of claim 15 , wherein the semantic level corresponds to a higher native semantic level in which function calls are replaced with high-level native opcodes.