Analog-to-digital converter speed calibration techniques
A conversion time and an acquisition time of an ADC can be estimated so that a speed of the ADC can be calibrated. An ADC circuit can perform M bit-trials in its conversion phase and continue performing additional bit-trials in a calibration mode. The ADC can count the number of additional bit-trials performed, e.g., X bit-trials, that occur before the next conversion phase, where additional bit-trials can be considered to be the number of available bit-trials during an acquisition time if the ADC continues performing bit-trials instead of sampling an input signal. The ADC can estimate the conversion time and the acquisition time using M and X. Then, the conversion time of the ADC can be calibrated by adjusting one or more of the comparison time, DAC settling delay, and logic propagation delay.
1. A method of calibrating a conversion speed of an asynchronous analog-to-digital converter (ADC) circuit, the method comprising:
at a time other than during an operational mode of the ADC circuit:
performing a number of bit-trials of a conversion on a received analog signal;
performing a number of additional bit-trials;
estimating a conversion time and an acquisition time using the number of bit-trials and the number of the additional bit-trials; and
adjusting an operational mode conversion time by adjusting bit-trial delays based on the estimated conversion time and the estimated acquisition time.
2. The method of claim 1 , wherein adjusting the operational mode conversion time includes:
adjusting a comparison time of a comparator circuit.
3. The method of claim 2 , wherein adjusting the comparison time of the comparator circuit includes:
adjusting a capacitance of the comparator circuit.
4. The method of claim 1 , wherein adjusting the operational mode conversion time includes:
adjusting a delay of a delay circuit.
5. The method of claim 4 , wherein adjusting the delay of the delay circuit includes:
adjusting a capacitance of the delay circuit.
6. The method of claim 1 , wherein adjusting the operational mode conversion time includes:
adjusting a logic circuit propagation delay.
7. The method of claim 1 , further comprising:
comparing the number of additional bit-trials to a threshold; and
to increase the conversion speed, decreasing the bit-trial delays when the number of additional bit-trials is less than the threshold.
8. The method of claim 1 , further comprising:
comparing the number of additional bit-trials to a threshold; and
to decrease the conversion speed, increasing the bit-trial delays when the number of additional bit-trials is greater than the threshold.
9. The method of claim 1 , further comprising:
iteratively repeating performing the number of bit-trials, performing and counting the number of additional bit-trials, the estimating, and adjusting until the number of additional bit-trials reaches a threshold.
10. The method of claim 1 , further comprising:
enabling a calibration mode that operates at a time other than a normal ADC operational mode.
11. The method of claim 1 , wherein performing a number of bit-trials includes:
performing successive approximation register (SAR) bit-trials.
12. An asynchronous analog-to-digital converter (ADC) circuit for calibrating a conversion speed, the circuit comprising:
a digital-to-analog converter circuit (DAC) configured to sample an analog signal; and
control circuitry coupled to the DAC, the control circuitry to:
at a time other than during an operational mode of the ADC circuit:
control the DAC to perform a number of bit-trials of a conversion on the sampled analog signal;
control the DAC to perform a number of additional bit-trials;
estimate a conversion time and an acquisition time using the number of bit-trials and the number of the additional bit-trials; and
adjust an operational mode conversion time by adjusting bit-trial delays based on the estimated conversion time and the estimated acquisition time.
13. The circuit of claim 12 , further comprising:
a comparator circuit, wherein the control circuitry configured to adjust the operational mode conversion time is configured to adjust a comparison time of the comparator circuit.
14. The circuit of claim 13 , wherein the control circuitry configured to adjust the operational mode conversion time is configured to adjust a capacitance of the comparator circuit.
15. The circuit of claim 12 , further comprising:
a delay circuit, wherein the control circuitry configured to adjust the operational mode conversion time is configured to adjusting a delay of the delay circuit.
16. The circuit of claim 15 , wherein the control circuitry configured to adjust the delay of the delay circuit is configured to adjust a capacitance of the delay circuit.
17. The circuit of claim 12 , wherein the control circuitry includes a logic circuit, and wherein the control circuitry configured to adjust the operational mode conversion time is configured to adjust a characteristic of the logic circuit.
18. The circuit of claim 12 , wherein the control circuitry is further configured to:
iteratively repeat performing the number of bit-trials, performing and counting the number of additional bit-trials, the estimating, and adjusting until the number of additional bit-trials reaches a threshold.
19. An asynchronous analog-to-digital converter (ADC) circuit for calibrating a conversion speed, the circuit comprising:
a digital-to-analog converter circuit (DAC) configured to sample an analog signal; and
control circuitry coupled to the DAC, the control circuitry to:
at a time other than during an operational mode of the ADC circuit:
control the DAC to perform a number of bit-trials of a conversion on the sampled analog signal;
control the DAC to perform a number of additional bit-trials; and
estimate a conversion time and an acquisition time using the number of bit-trials and the number of the additional bit-trials; and
means for adjusting an operational mode conversion time by adjusting bit-trial delays based on the estimated conversion time and the estimated acquisition time.
20. The circuit of claim 19 , wherein the control circuitry includes successive approximation register (SAR) control circuitry.