Clock signal control
Clock signal control circuitry comprises a clock selector to output a current clock signal selected from two or more candidate clock signals and to execute a clock signal change operation to select a different one of the two or more candidate clock signals for output as the current clock signal; a counter to generate a count value by counting clock pulses of the current clock signal multiplied by a scaling value; and control logic to execute a scaling value change operation to change the scaling value in response to initiation of a clock signal change operation; in which the clock selector and the control logic are configured to cooperate to inhibit the output of the current clock signal during a scaling value change operation.
1. Clock signal control circuitry comprising:
a clock selector to output a current clock signal selected from two or more candidate clock signals and to execute a clock signal change operation to select a different one of the two or more candidate clock signals for output as the current clock signal;
a counter to generate a count value by counting clock pulses of the current clock signal multiplied by a scaling value; and
control logic to execute a scaling value change operation to change the scaling value in response to initiation of a clock signal change operation;
wherein the clock selector and the control logic are configured to cooperate to inhibit the output of the current clock signal during a scaling value change operation.
2. Circuitry according to claim 1 , wherein the clock selector is configured to inhibit the output of the current clock signal during a clock signal change operation.
3. Circuitry according to claim 1 , comprising:
scaling value storage to store two or more candidate scaling values;
the control logic is configured, as at least a part of a scaling value change operation, to provide a selected one of the candidate scaling values to the counter.
4. Circuitry according to claim 1 , configured to temporarily inhibit operation of the counter during a storage process of storing the two or more candidate scaling values in the scaling value storage.
5. Circuitry according to claim 1 , comprising:
clock generation circuitry to generate the candidate clock signals;
wherein the clock generation circuitry is configured to define the clock frequencies of the candidate clock signals and to generate the candidate scaling values.
6. Circuitry according to claim 1 , wherein:
a respective candidate scaling value corresponds to each of the two or more candidate clock signals; and
the candidate scaling values vary in inverse proportion to the clock frequency of the respective candidate clock signals.
7. Circuitry according to claim 1 , wherein the control logic is configured to operate in response to a clock signal which continues during at least a scaling value change operation.
8. Data processing circuitry comprising
circuitry according to claim 1 ;
a processing element to execute successive program instructions; and
count processing circuitry to perform a data processing action in response to the count value.
9. Data processing circuitry according to claim 7 , wherein the data processing action comprises one or more of:
initiating a processor interrupt;
initiating a reset of the processing element;
initiating a change in program flow;
associating a timestamp with a sensor data packet indicative of a sensor detection; and
associating a timestamp with a debug data packet indicative of a current state of the processing element.
10. Clock signal control circuitry comprising:
means for selecting and outputting a current clock signal from two or more candidate clock signals;
means for executing a clock signal change operation to select a different one of the two or more candidate clock signals for output as the current clock signal;
means for generating a count value by counting clock pulses of the current clock signal multiplied by a scaling value;
means for executing a scaling value change operation to change the scaling value in response to initiation of a clock signal change operation; and
means for inhibiting the output of the current clock signal during a scaling value change operation.
11. A method comprising:
selecting and outputting a current clock signal from two or more candidate clock signals;
executing a clock signal change operation to select a different one of the two or more candidate clock signals for output as the current clock signal;
generating a count value by counting clock pulses of the current clock signal multiplied by a scaling value;
executing a scaling value change operation to change the scaling value in response to initiation of a clock signal change operation; and
inhibiting the output of the current clock signal during a scaling value change operation.