Flyback converter with multiplier signal control circuit and method
A multiplier signal, and multiplier circuits and methods are provided to improve the total harmonic distortion (THD) and power factor (PF) for a flyback type power factor correction (PFC) circuit. The multiplier signal has a “pulled-up” waveshape that is configured to compensate for the “push-down” effect of varying off times of an electronic switch of the PFC on a line current of the PFC. The multiplier circuit is configured to reduce the multiplier signal during a first operational mode of the multiplier circuit and is further configured to maintain a typical multiplier signal during a second operational mode. The first operational mode occurs before a first phase angle and after a second phase angle during each half-cycle of a power source coupled to the PFC circuit. The second operational mode occurs between the first and second phase angles during each half-cycle.
1. A power supply comprising:
a direct current (DC) power source coupled to receive input power from an alternating current (AC) power source and configured to provide a DC power across first and second lines;
an energy storage device coupled across the first and second lines; and
a power factor correction (PFC) circuit coupled across the first and second lines, and comprising:
an inductive element having a first end coupled to a first end of the energy storage device;
a controlled switching element coupled between a second end of the inductive element and the second line;
an integrated circuit (IC) configured to control on-times and off-times of the switching element and thereby a current through the inductive element in response to a multiplier signal received at a multiplier signal input of the IC; and
a multiplier circuit comprising a switching device and configured to define the multiplier signal to the multiplier signal input by switching between a first operational mode of the multiplier circuit and a second operational mode of the multiplier circuit during each half-cycle of the DC power, wherein the multiplier signal is provided as an ideal sinusoid corresponding to a shape of the input power from the AC power source independently of varying off-times of the PFC switching element.
2. The power supply of claim 1 , wherein the multiplier signal is modified to push down a waveform shape of the current through the inductive element during the first operational mode, wherein a total harmonic distortion (THD) of the PFC circuit is reduced.
3. The power supply of claim 1 , wherein:
the first operational mode of the multiplier circuit is associated with a voltage across the energy storage device being below a threshold voltage; and
the second operational mode of the multiplier circuit is associated with the voltage across the energy storage device being above the threshold voltage.
4. The power supply of claim 1 , wherein:
the DC power across the first and second lines includes a DC voltage waveform;
the first operational mode of the multiplier circuit occurs before a first phase angle of the DC voltage waveform and after a second phase angle of the DC voltage waveform during each half-cycle of the DC power; and
the second operational mode of the multiplier circuit occurs between the first and second phase angles of the DC voltage waveform during each half-cycle of the DC power.
5. The power supply of claim 1 , wherein:
the multiplier circuit includes a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, and the switching device configured to switch between the first operational mode and the second operational mode during each half-cycle of the DC power; and
the first operational mode associated with the switching device being off and the second operational mode associated with the switch being on.
6. The power supply of claim 5 , wherein:
the switching device comprising a base node, a collector node, and an emitter node coupled to the multiplier signal input terminal;
the first resistor is coupled between the first line and the collector node;
the second resistor is coupled between the emitter node and the second line;
the third resistor is coupled between collector node and the emitter node;
the fourth resistor coupled between the first line and the base node; and
the fifth resistor coupled between the base node and the second line.
7. The power supply of claim 6 , wherein:
the first, second, and third resistors are coupled in series when the multiplier circuit is in the first operational mode; and
the third resistor is short circuited when the multiplier circuit is in the second operational mode.
8. The power supply of claim 1 , wherein:
the multiplier circuit includes a first resistor and the switching device comprises a Zener diode coupled between the first line and the multiplier signal input terminal; and
the multiplier circuit includes a second resistor coupled between the multiplier signal input terminal and the second line.
9. The power supply of claim 8 , wherein:
the Zener diode is associated with a Zener voltage;
the multiplier circuit operates in the first operational mode when the voltage across the capacitor is below the Zener voltage; and
the multiplier circuit operates in the second operational mode when the voltage across the capacitor is above the Zener voltage.
10. The power supply of claim 1 , wherein:
the multiplier circuit includes a first resistor, a second resistor, a third resistor, and the switching device comprises a DIAC;
the first resistor is coupled to the first line;
the DIAC and the third resistor are coupled in parallel between the first resistor and the multiplier signal input terminal; and
the second resistor is coupled between the multiplier signal input terminal and the second line.
11. The power supply of claim 10 , wherein:
the DIAC is associated with a breakdown voltage;
the multiplier circuit operates in the first operational mode when the voltage across the capacitor is below the breakdown voltage; and
the multiplier circuit operates in the second operational mode when the voltage across the capacitor is above the breakdown voltage.
12. The power supply of claim 11 , wherein:
the DIAC operates as an open circuit during the first operational mode; and
the DIAC short circuits the third resistor during the second operational mode.
13. The power supply of claim 1 , wherein:
the multiplier signal includes a multiplier signal waveform shape defined during each half-cycle of the DC power;
a beginning portion and an end portion of the multiplier signal waveform shape is defined during the first operational mode of the multiplier circuit; and
a middle portion of the multiplier signal waveform shape is defined during the second operational mode of the multiplier circuit.
14. A multiplier circuit for coupling across first and second input lines of a power factor correction (PFC) circuit and to a multiplier input of an integrated circuit (IC) of the PFC circuit, the multiplier circuit comprising:
a first resistor coupled between the first input line and the multiplier input;
a second resistor coupled between the multiplier input and the second input line, the second resistor configured to define a multiplier voltage for transmission to the multiplier input of the IC of the PFC circuit, the multiplier voltage having a multiplier voltage waveform which repeats during each half-cycle of an input voltage receivable across the first and second input lines of the PFC; and
a switching circuit configured to reduce the multiplier voltage prior to a first phase angle associated with each half cycle and after a second phase angle associated with each half-cycle,
wherein the first and second resistors operate in series as a voltage divider between the first and second input lines of the PFC between the first phase angle and the second phase angle during each half-cycle.
15. The multiplier circuit of claim 14 , wherein:
the switching circuit includes a first voltage divider resistor, a second voltage divider resistor, a third voltage divider resistor, and an electronic switch;
the first voltage divider resistor coupled between the first input line and a base terminal of the electronic switch;
the second voltage divider resistor coupled between the base terminal and the second input line;
the first resistor is coupled between the first input line and a collector terminal of the electronic switch;
the second resistor is coupled between an emitter terminal of the electronic switch and the second input line.
16. The multiplier circuit of claim 14 , wherein:
the electronic switch includes a threshold voltage;
below the threshold voltage the third voltage divider resistor operates in series with the first and second resistors; and
above the threshold voltage the third voltage divider resistor is bypassed by the electronic switch.
17. The multiplier circuit of claim 14 , wherein:
the switching circuit includes a Zener diode coupled between the first resistor and the multiplier input;
the Zener diode having a larger effective resistance when a voltage across the Zener diode is lower than a Zener voltage of the Zener diode.
18. The multiplier circuit of claim 14 , wherein:
the switching circuit includes a DIAC and a voltage divider resistor coupled in parallel;
the DIAC and the voltage divider resistor coupled between the first resistor and the multiplier input;
a current exclusively flows through the voltage divider resistor when a voltage across the multiplier circuit is below a breakdown voltage of the DIAC; and
the current exclusively flows through the DIAC when the voltage across the multiplier circuit is above the breakdown voltage of the DIAC.
19. A method of improving a total harmonic distortion (THD) of a line current received by a power factor correction (PFC) circuit, the method comprising:
generating a reduced multiplier signal voltage prior to a first phase angle of the line current and after a second phase angle of the line current during each half cycle of the line current; and
generating an unaltered/normal multiplier signal voltage between the first phase angle and the second phase angle during each half-cycle of the line current.