IP Library Granted Patent US 10,678,321
Granted Patent B2
US 10,678,321 · App. 16/116,053 · Granted Jun 9, 2020

Systems and methods for reduced boot power consumption using early BIOS controlled CPU P-states to enhance power budgeting and allocation

Inventors: Doug E. Messick (Austin, TX); Jordan Chin (Austin, TX); Rui Shi (Cedar Park, TX); Kyle E. Cross (Austin, TX)
Assignee: Dell Products L.P.
G06F1/3234G06F9/4401
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Quick Facts
Patent No.
US 10,678,321
App. No.
16/116,053
Granted
Jun 9, 2020
Kind
B2
Abstract

Systems and methods for reduced boot power consumption using early BIOS controlled CPU power states to enhance power budgeting and allocation. An information handling system may include a server. The server may include a central processing unit (CPU), a memory, a non-volatile random-access memory (NVRAM) device, a performance state (P-state) limiting indicator stored in the NVRAM device, a P-state value stored in the NVRAM, and a basic input/output system (BIOS) stored in the memory. The BIOS may read a power state limiting indicator stored in the NVRAM device and when the power state limiting indicator indicates that power state limiting is enabled, read a power state value stored in the NVRAM, and program the power state of the CPU to the power state value to cause the CPU to limit power supplied to the CPU to the power state value.

Claims (94)

1. An information handling system (IHS), comprising:

a first server comprising:

a first central processing unit (CPU);

a memory;

a non-volatile random-access memory (NVRAM) device;

a first performance state (P-state) limiting indicator stored in the NVRAM device;

a first P-state value stored in the NVRAM; and

a basic input/output system (BIOS) stored in the memory and operable when executed by the first CPU to:

read a first power state limiting indicator stored in the NVRAM device; and

when the first power state limiting indicator indicates that power state limiting is enabled:

read a first power state value stored in the NVRAM; and

program the power state of the first CPU to the first power state value to cause the first CPU to limit power supplied to the first CPU to less than or equal to the first power state value; and

when a BIOS checkpoint event occurs during execution of the BIOS:

the first CPU ceases to limit CPU power supplied to the first CPU,

wherein the BIOS checkpoint event occurs after the power state of the first CPU has been programmed.

2. The information handling system of claim 1 , wherein the first server further comprises:

a first system management controller to, when power state limiting is enabled, calculate an optimal first boot power allocation (BPA) value and a first range of BPA values based on a power capability of the first server, wherein the optimal first BPA value is within the first range of BPA values, and wherein the first power state value stored in the NVRAM is the calculated optimal BPA value.

3. The information handling system of claim 1 , wherein the first server further comprises:

a first system management controller to:

calculate an optimal BPA value based on a power capability of the first server;

read a user power cap value stored in the NVRAM;

calculate a minimum power state value as the minimum of the calculated optimal BPA value and the user power cap value, wherein the first power state value stored in the NVRAM is the minimum power state value.

4. The information handling system of claim 1 , wherein, when the first power state limiting indicator indicates that power state limiting is disabled, the power supplied to the first CPU is unconstrained.

5. The information handling system of claim 1 , wherein the BIOS further operable when executed by the first CPU to, when the first power state limiting indicator indicates that power state limiting is disabled:

read a second power state limiting indicator stored in the NVRAM device; and

when the second power state limiting indicator indicates that power state limiting is enabled:

read a second power state value stored in the NVRAM; and

program the power state of the first CPU to the second power state value to cause the first CPU to limit power supplied to the first CPU to less than or equal to the second power state value, wherein the second power state value is greater than the first power state value.

6. The information handling system of claim 1 , wherein the information handling system further comprises:

a second server; and

a chassis management controller to:

when power state limiting transitions from enabled to disabled:

re-allocate the power supplied to the first server from a first optimized BPA value to a first BPA value; and

re-allocate the power supplied to the second server from a second optimized BPA value to a second BPA value; and

when power state limiting transitions from disabled to enabled:

re-allocate the power supplied to the first server from the first BPA value to the first optimized BPA; and

re-allocate the power supplied to the second server from the second BPA value to the second optimized BPA value, wherein the first optimized BPA value is less than the first BPA value, and wherein the second optimized BPA value is less than the second BPA value.

7. The information handling system of claim 1 , wherein the first server further comprises:

a first system management controller to calculate an optimal first BPA value and a first range of BPA values based on a power capability of the first server, and

wherein the information handling system further comprises:

a second server comprising:

a second CPU; and

a second system management controller to calculate an optimal second BPA value and a second range of BPA values based on a power capability of the second server; and

a chassis management controller to, when power state limiting is enabled:

receive the optimal first BPA value and the first range of BPA values from the first system management controller;

receive the optimal second BPA value and the second range BPA values from the second system management controller;

calculate a third BPA value for the first server and a fourth BPA value for the second server based on a chassis power budget, the optimal first BPA value, the first range of BPA values, the optimal second BPA value, and the second range of BPA values, wherein the third BPA value is within the first range of BPA values and the fourth BPA value is within the second range of BPA values;

send the third BPA value to the first system management controller, wherein, when power state limiting is enabled, the power supplied to the first CPU is limited to the third BPA value; and

send the fourth BPA value to the second system management controller, wherein, when power state limiting is enabled, the power supplied to the second CPU is limited to the fourth BPA value.

8. The information handling system of claim 7 , wherein the third BPA value is less than the optimal first BPA value.

9. The information handling system of claim 7 , wherein the chassis management controller further to:

receive a user power cap value from a user interface of the chassis management controller, wherein the calculation of the third BPA value and the fourth BPA value is further based on the user power cap value, and wherein the sum of the third BPA value and the fourth BPA value is less than or equal to the user power cap value.

10. The information handling system of claim 9 , wherein the user power cap value is less than the sum of the power capability of the first server and the power capability of the second server.

11. A method, comprising:

reading, by a basic input/output system (BIOS) of a first server of an information handling system, a first power state limiting indicator stored in a first non-volatile random-access memory (NVRAM) device of the first server; and

when the first power state limiting indicator indicates that power state limiting is enabled:

reading, by the BIOS, a first power state value stored in the NVRAM; and

programming, by the BIOS, a power state of a first central processing unit (CPU) of the first server to the first power state value to cause the first CPU to limit power supplied to the first CPU to less than or equal to the first power state value; and

when a BIOS checkpoint event occurs during the BIOS:

ceasing, by the first CPU, to limit CPU power supplied to the first CPU,

wherein the BIOS checkpoint event occurs after the power state of the first CPU has been programmed.

12. The method of claim 11 , wherein the method further comprises:

when power state limiting is enabled, calculating, by a first system management controller of the first server, an optimal first boot power allocation (BPA) value and a first range of BPA values based on a power capability of the first server, wherein the optimal first BPA value is within the first range of BPA values, and wherein the first power state value stored in the NVRAM is the calculated optimal BPA value.

13. The method of claim 11 , wherein the method further comprises:

calculating, by a first system management controller of the first server, an optimal BPA value based on a power capability of the first server;

reading, by the first system management controller, a user power cap value stored in the NVRAM;

calculating, by the first system management controller, a minimum power state value as the minimum of the calculated optimal BPA value and the user power cap value, wherein the first power state value stored in the NVRAM is the minimum power state value.

14. The method of claim 11 , wherein, when the first power state limiting indicator indicates that power state limiting is disabled, the power supplied to the first CPU is unconstrained.

15. The method of claim 11 , wherein the method further comprises, when the first power state limiting indicator indicates that power state limiting is disabled:

reading, by the BIOS, a second power state limiting indicator stored in the NVRAM device; and

when the second power state limiting indicator indicates that power state limiting is enabled:

reading, by the BIOS, a second power state value stored in the NVRAM; and

programming, by the BIOS, the power state of the first CPU to the second power state value to cause the first CPU to limit power supplied to the first CPU to less than or equal to the second power state value, wherein the second power state value is greater than the first power state value.

16. The method of claim 11 , wherein the method further comprises:

when power state limiting transitions from enabled to disabled:

re-allocating, by a chassis management controller of the information handling system, the power supplied to the first server from a first optimized BPA value to a first BPA value; and

re-allocating, by the chassis management controller, the power supplied to a second server of the information handling system from a second optimized BPA value to a second BPA value; and

when power state limiting transitions from disabled to enabled:

re-allocating, by the chassis management controller, the power supplied to the first server from the first BPA value to the first optimized BPA; and

re-allocating, by the chassis management controller, the power supplied to the second server from the second BPA value to the second optimized BPA value, wherein the first optimized BPA value is less than the first BPA value, and wherein the second optimized BPA value is less than the second BPA value.

17. The method of claim 11 , wherein the method further comprises:

calculating, by a first system management controller of the first server, an optimal first BPA value and a first range of BPA values based on a power capability of the first server;

a second CPU; and

calculating, by a second system management controller of a second server, an optimal second BPA value and a second range of BPA values based on a power capability of the second server; and

when power state limiting is enabled:

receiving, by a chassis management controller of the information handling system, the optimal first BPA value and the first range of BPA values from the first system management controller;

receiving, by the chassis management controller, the optimal second BPA value and the second range BPA values from the second system management controller;

calculating, by the chassis management controller, a third BPA value for the first server and a fourth BPA value for the second server based on a chassis power budget, the optimal first BPA value, the first range of BPA values, the optimal second BPA value, and the second range of BPA values, wherein the third BPA value is within the first range of BPA values and the fourth BPA value is within the second range of BPA values;

sending, by the chassis management controller, the third BPA value to the first system management controller, wherein, when power state limiting is enabled, the power supplied to the first CPU is limited to the third BPA value; and

sending, by the chassis management controller, the fourth BPA value to the second system management controller, wherein, when power state limiting is enabled, the power supplied to the second CPU is limited to the fourth BPA value.

18. The method of claim 17 , wherein the third BPA value is less than the optimal first BPA value.

19. The method of claim 17 , wherein the method further comprising:

receiving, by the chassis management controller, a user power cap value from a user interface of the chassis management controller, wherein the calculation of the third BPA value and the fourth BPA value is further based on the user power cap value, and wherein the sum of the third BPA value and the fourth BPA value is less than or equal to the user power cap value.

20. The method of claim 19 , wherein the user power cap value is less than the sum of the power capability of the first server and the power capability of the second server.

Assignments (5)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (053546/0001) Recorded Jun 23, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL MARKETING L.P. (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO CREDANT TECHNOLOGIES, INC.); DELL INTERNATIONAL L.L.C.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO FORCE10 NETWORKS, INC. AND WYSE TECHNOLOGY L.L.C.); EMC IP HOLDING COMPANY LLC
Reel/Frame 071642/0001 →
SECURITY AGREEMENT Recorded Oct 1, 2021
From: DELL PRODUCTS, L.P.; EMC IP HOLDING COMPANY LLC
To: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
Reel/Frame 057682/0830 →
SECURITY AGREEMENT Recorded Apr 22, 2020
From: CREDANT TECHNOLOGIES INC.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; FORCE10 NETWORKS, INC.; WYSE TECHNOLOGY L.L.C.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.
Reel/Frame 053546/0001 →
SECURITY AGREEMENT Recorded Mar 21, 2019
From: CREDANT TECHNOLOGIES, INC.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; FORCE10 NETWORKS, INC.; WYSE TECHNOLOGY L.L.C.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.
Reel/Frame 049452/0223 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 29, 2018
From: MESSICK, DOUG E.; CHIN, JORDAN; SHI, RUI; CROSS, KYLE E.
To: DELL PRODUCTS L.P.
Reel/Frame 046740/0232 →