Bootstrapped switch circuit with improved speed
A bootstrapped switch circuit includes an auxiliary loop circuit for assisting the boosting of a bootstrap voltage in a main loop circuit having a bootstrapped switch transistor. The boosted bootstrap voltage switches on the bootstrapped switch transistor so that an input voltage signal may conduct through the bootstrapped switch transistor to charge a sampling node.
1. A bootstrapped switch circuit comprising:
a main loop circuit including:
a bootstrap capacitor;
a bootstrapped switch transistor coupled between a node for an input voltage signal and a sampling node for the input voltage signal;
a first loop transistor coupled between a positive terminal of the bootstrap capacitor and a gate of the bootstrapped switch transistor; and
a second loop transistor coupled between the node for the input voltage signal and a negative terminal of the bootstrap capacitor; and
an auxiliary loop circuit configured to assert a replica bootstrap voltage for controlling a switching of the second loop transistor, wherein the auxiliary loop circuit comprises
a replica bootstrap capacitor,
a replica first loop transistor,
a replica second loop transistor coupled between the node for the input voltage signal and a negative terminal of the replica bootstrap capacitor, wherein the replica first loop transistor is coupled between a positive terminal of the replica bootstrap capacitor and a gate of the replica second loop transistor,
a first PMOS transistor having a source connected to a node of a power supply voltage, and
a first NMOS transistor having a source connected to the negative terminal of the replica bootstrap capacitor and a drain connected to a drain of the first PMOS transistor, wherein the drain of the first PMOS transistor and the drain of the first NMOS transistor are both connected to a gate of the replica first loop transistor.
2. The bootstrapped switch circuit of claim 1 , wherein the main loop circuit further includes a third loop transistor coupled between the first loop transistor and the gate of the bootstrapped switch transistor.
3. The bootstrapped switch circuit of claim 1 , wherein the main loop circuit further includes an inverter configured to invert a clock signal to control a switching of the first loop transistor.
4. The bootstrapped switch circuit of claim 1 , wherein the replica first loop transistor and the replica second loop transistor are both smaller than the first loop transistor and the second loop transistor.
5. The bootstrapped switch circuit of claim 1 , wherein a node for a clock signal is connected to a gate for the first PMOS transistor and to a gate for the first NMOS transistor, the auxiliary loop circuit further including a second NMOS transistor having a drain connected to the gate of the first loop transistor and a source connected to the negative terminal of the replica bootstrap capacitor.
6. The bootstrapped switch circuit of claim 1 , wherein the auxiliary loop circuit further includes an inverter configured to discharge the replica bootstrap voltage.
7. The bootstrapped switch circuit of claim 6 , wherein the main loop circuit is configured to discharge the bootstrap voltage prior to the discharge of the replica bootstrap voltage.
8. The bootstrapped switch circuit of claim 6 , wherein the main loop circuit if configured to discharge the bootstrap voltage after the discharge of the replica bootstrap voltage.
9. The bootstrapped switch circuit of claim 1 , wherein the sampling node is a terminal of a capacitor for a digital-to-analog-converter.
10. The bootstrapped switch circuit of claim 1 , wherein the bootstrapped switch circuit is incorporated into a cellular telephone.
11. The bootstrapped switch circuit of claim 1 , further comprising:
a switched capacitor circuit configured to control a charging of the bootstrap capacitor.
12. The bootstrapped switch circuit of claim 11 , wherein the switched capacitor circuit is further configured to control a charging of a replica bootstrap capacitor in the auxiliary loop circuit.