Efficiency improvement for a DC-to-DC buck voltage regulator

1. A circuit comprising:

a first driver having an input, an output and a power input;

a first regulator having an input, an output coupled to the first driver, and an adjustment control configured to control a voltage of the first regulator;

a gate control coupled to the first driver, the gate control configured to receive a pulse width modulation input, and wherein the voltage of the first regulator is selected as a function of the pulse width modulation input;

a second driver having an input, an output and a power input;

a second regulator having an input, an output coupled to the second driver, and an adjustment control configured to control a voltage of the second regulator; and

a first impedance coupled to the adjustment control of the first regulator and configured to selectably increase or decrease the voltage of the first regulator.

2. The circuit of claim 1 further comprising a second impedance coupled to the adjustment control of the second regulator and configured to selectably increase or decrease the voltage of the second regulator.

3. The circuit of claim 2 further comprising a third impedance coupled to the second impedance.

4. The circuit of claim 2 further comprising a third impedance coupled to the adjustment control of the second regulator.

5. The circuit of claim 1 further comprising a second impedance coupled to the first impedance.

6. The circuit of claim 1 further comprising a second impedance coupled to the adjustment control of the first regulator.

7. The circuit of claim 1 further comprising a gate control coupled to the second driver, the gate control configured to receive a pulse width modulation input, and wherein the voltage of the second regulator is selected as a function of the pulse width modulation input.

8. The circuit of claim 1 further comprising a second impedance coupled to the first impedance and a third impedance coupled to the adjustment control of the first regulator.

9. The circuit of claim 1 further comprising:

a gate control coupled to the second driver, the gate control configured to receive a pulse width modulation input, and wherein the voltage of the second regulator is selected as a function of the pulse width modulation input; and

a second impedance coupled to the first impedance.

10. A method for controlling a circuit, comprising:

receiving a pulse width modulation signal at a first gate control to generate a first gate control signal;

receiving the first gate control signal at a first driver to generate a first output;

adjusting a resistance coupled to an input of a first regulator to control an output voltage of the first regulator that is provided to the first driver;

receiving the pulse width modulation signal at a second gate control to generate a second gate control signal;

receiving the second gate control signal at a second driver to generate a second output; and

adjusting a resistance coupled to an input of a second regulator to control an output voltage of the second regulator that is provided to the second driver.

11. The method of claim 10 further comprising selectably increasing or decreasing the output voltage of the first regulator.

12. The method of claim 11 further comprising selectably increasing or decreasing the output voltage of the second regulator.

13. The method of claim 10 further comprising selectably increasing or decreasing the output voltage of the second regulator.

14. The method of claim 10 further comprising:

determining an optimal setting for the output voltage of the first regulator; and

adjusting the resistance coupled to the input of the first regulator to control the output voltage of the first regulator to the optimal setting for the output voltage of the first regulator.

15. The method of claim 14 further comprising:

determining an optimal setting for the output voltage of the second regulator; and

adjusting the resistance coupled to the input of the second regulator to control the output voltage of the second regulator to the optimal setting for the output voltage of the second regulator, wherein the optimal setting for the output voltage of the first regulator is different from the optimal setting for the output voltage of the second regulator.

16. The method of claim 15 wherein determining the optimal setting for the output voltage of the first regulator is performed as a first function of a pulse width modulation duty cycle and determining the optimal setting for the output voltage of the second regulator is performed as a second function of the pulse width modulation duty cycle.

17. The method of claim 14 wherein determining the optimal setting for the output voltage of the first regulator is performed as a function of a pulse width modulation duty cycle.

18. The method of claim 10 further comprising:

determining an optimal setting for the output voltage of the second regulator; and

adjusting the resistance coupled to the input of the second regulator to control the output voltage of the second regulator to the optimal setting for the output voltage of the second regulator.

19. The method of claim 18 wherein determining the optimal setting for the output voltage of the second regulator is performed as a function of a pulse width modulation duty cycle.

20. In a circuit comprising a first driver having an input, an output and a power input, a first regulator having an input, an output coupled to the first driver, and an adjustment control configured to control a voltage of the first regulator, a second driver having an input, an output and a power input, a second regulator having an input, an output coupled to the second driver, and an adjustment control configured to control a voltage of the second regulator, a first impedance coupled to the adjustment control of the first regulator and configured to selectably increase or decrease the voltage of the first regulator, a second impedance coupled to the adjustment control of the second regulator and configured to selectably increase or decrease the voltage of the second regulator, the second impedance coupled to the first impedance and to the adjustment control of the first regulator, a third impedance coupled to the second impedance and to the adjustment control of the second regulator, a gate control coupled to the first driver, the gate control configured to receive a pulse width modulation input, and wherein the voltage of the first regulator is selected as a function of the pulse width modulation input, the gate control coupled to the second driver, the gate control configured to receive a pulse width modulation input, and wherein the voltage of the second regulator is selected as a function of the pulse width modulation input, a method comprising:

receiving a pulse width modulation signal at a first gate control to generate a first gate control signal;

receiving the first gate control signal at a first driver to generate a first output;

adjusting a resistance coupled to an input of a first regulator to control an output voltage of the first regulator that is provided to the first driver;

receiving the pulse width modulation signal at a second gate control to generate a second gate control signal;

receiving the second gate control signal at a second driver to generate a second output;

adjusting a resistance coupled to an input of a second regulator to control an output voltage of the second regulator that is provided to the second driver

selectably increasing or decreasing the output voltage of the first regulator;

selectably increasing or decreasing the output voltage of the second regulator;

determining an optimal setting for the output voltage of the first regulator;

adjusting the resistance coupled to the input of the first regulator to control the output voltage of the first regulator to the optimal setting for the output voltage of the first regulator;

determining an optimal setting for the output voltage of the second regulator;

adjusting the resistance coupled to the input of the second regulator to control the output voltage of the second regulator to the optimal setting for the output voltage of the second regulator, wherein the optimal setting for the output voltage of the first regulator is different from the optimal setting for the output voltage of the second regulator, wherein determining the optimal setting for the output voltage of the first regulator is performed as a first function of a pulse width modulation duty cycle and determining the optimal setting for the output voltage of the second regulator is performed as a second function of the pulse width modulation duty cycle.