IP Library Granted Patent US 10,691,595
Granted Patent B2
US 10,691,595 · App. 16/108,037 · Granted Jun 23, 2020

Cache in a non-volatile memory subsystem

Inventors: Robert M. Walker (Raleigh, NC); Ashay Narsale (Newark, CA)
Assignee: MICRON TECHNOLOGY, INC.
G06F12/0804G06F12/0811G06F12/128G06F13/1605G06F2212/222
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Quick Facts
Patent No.
US 10,691,595
App. No.
16/108,037
Granted
Jun 23, 2020
Kind
B2
Abstract

A first request to perform an operation at an address associated with a media is obtained. The operation is issued to a plurality of cache divisions, wherein each cache division comprises a cache controller and a cache memory. A location in another memory associated with the first request is updated, the location in the other memory including a plurality of indicators corresponding to a status of the operation with each of the plurality of cache divisions. Based on one or more responses from the cache division(s), a response to the first request is sent.

Claims (42)

1. A method comprising:

obtaining a first request to perform an operation at an address associated with a media;

issuing the operation to a plurality of cache divisions, wherein each cache division comprises a cache controller and a cache memory;

updating a location in another memory associated with the first request, the location in the other memory including a plurality of indicators corresponding to a status of the operation with each of the plurality of cache divisions, the updating including using one of the plurality of indicators to mark a corresponding cache division as checked in the performance of the operation; and

sending a response to the first request.

2. The method of claim 1 , wherein the response is sent prior to completing the operation with a first cache division in the plurality of cache divisions.

3. The method of claim 1 , further comprising arbitrating for access to issue the operation to each of the cache controllers within the plurality of cache divisions.

4. The method of claim 1 , further comprising writing to a selected location in a first cache division in the plurality of cache divisions when the plurality of indicators in the location in the other memory indicate that a check of each cache division resulted in a miss.

5. The method of claim 4 , further comprising selecting, based on a cache replacement policy, the selected location.

6. The method of claim 4 , wherein the writing comprises arbitrating for access to the first cache division.

7. The method of claim 4 , wherein prior to writing to the selected location:

identifying the selected location within the first cache division;

reading the selected location to obtain another address associated with the media, cached data, and a dirty bit; and

in response to the dirty bit being set, writing the cached data to the other address associated with the media.

8. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to:

obtain a first request to perform an operation at an address associated with a media;

issue the operation to a plurality of cache divisions, wherein each cache division comprises a cache controller and a cache memory;

update a location in another memory associated with the first request, the location in the other memory including a plurality of indicators corresponding to a status of the operation with each of the plurality of cache divisions, the updating including using one of the plurality of indicators to mark a corresponding cache division as checked in the performance of the operation; and

send a response to the first request.

9. The non-transitory computer-readable storage medium of claim 8 , wherein the response is sent prior to completing the operation with a first cache division in the plurality of cache divisions.

10. The non-transitory computer-readable storage medium of claim 8 , wherein the processing device is further to arbitrate for access to issue the operation to each of the cache controllers within the plurality of cache divisions.

11. The non-transitory computer-readable storage medium of claim 8 , wherein the processing device is further to write to a selected location in a first cache division in the plurality of cache divisions when the plurality of indicators in the location in the other memory indicate that a check of each cache division resulted in a miss.

12. The non-transitory computer-readable storage medium of claim 11 , wherein the processing device is further to select, based on a cache replacement policy, the selected location.

13. The non-transitory computer-readable storage medium of claim 11 , wherein the processing device is further to arbitrate for access to the first cache division to write to the selected location.

14. The non-transitory computer-readable storage medium of claim 11 , wherein prior to writing to the selected location:

identifying the selected location within the first cache division;

reading the selected location to obtain another address associated with the media, cached data, and a dirty bit; and

in response to the dirty bit being set, writing the cached data to the other address associated with the media.

15. A system comprising:

a plurality of memory components; and

a processing device, operatively coupled with the plurality of memory components, to:

obtain a first request to perform an operation at an address associated with a media;

adding the first request to a queue of requests;

issue, based on a scheduling policy, the operation to a plurality of cache divisions, wherein each cache division comprises a cache controller and a cache memory;

update a location in another memory associated with the first request in the queue of requests, the location in the other memory including a plurality of indicators corresponding to a status of the operation with each of the plurality of cache divisions, the updating including using one of the plurality of indicators to mark a corresponding cache division as checked in the performance of the operation;

send a response to the first request; and

removing the first request from the queue of requests.

16. The system of claim 15 , wherein the response is sent prior to completing the operation with a first cache division in the plurality of cache divisions.

17. The system of claim 15 , wherein the processing device is further to arbitrate for access to issue the operation to each of the cache controllers within the plurality of cache divisions.

18. The system of claim 15 , wherein the processing device is further to write to a selected location in a first cache division in the plurality of cache divisions when the plurality of indicators in the location in the other memory indicate that a check of each cache division resulted in a miss.

19. The system of claim 18 , wherein the processing device is further to select, based on a cache replacement policy, the selected location.

20. The system of claim 18 , wherein the processing device is further to arbitrate for access to the first cache division to write to the selected location.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Nov 14, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 051028/0835 →
RELEASE OF SECURITY INTEREST Recorded Oct 14, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050719/0550 →
SUPPLEMENT NO. 1 TO PATENT SECURITY AGREEMENT Recorded Nov 13, 2018
From: MICRON TECHNOLOGY, INC.
To: JPMORGAN CHASE BANK, N.A.., AS COLLATERAL AGENT
Reel/Frame 047630/0756 →
SUPPLEMENT NO. 10 TO PATENT SECURITY AGREEMENT Recorded Nov 13, 2018
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 048102/0420 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 22, 2018
From: WALKER, ROBERT M.; NARSALE, ASHAY
To: MICRON TECHNOLOGY, INC
Reel/Frame 046662/0757 →