Memory system for error test
A memory system includes: a memory controller configured to control communication between a host and a memory device; and an error test device configured to store error operation codes for generating errors, wherein the error test device outputs the error operation codes to the memory controller under the control of the memory controller, and wherein the memory controller determines whether an error has been generated in any operation corresponding to any of the error operation codes, and, when it is determined that an error has been generated, the memory controller stores one or more error requests corresponding to the generated error.
1. A memory system comprising:
a memory controller configured to control communication between a host and a memory device; and
an error test device configured to store error operation codes which are generated on a result obtained by performing test operations of the memory system,
wherein the error test device outputs the error operation codes to the memory controller under the control of the memory controller, and
wherein the memory controller tests the memory device by transferring the error operation codes to the memory device, determines whether an error has been generated in any operation corresponding to any of the error operation codes, and, when it is determined that an error has been generated, the memory controller stores one or more error requests corresponding to the generated error.
2. The memory system of claim 1 , wherein the error test device includes an error operation code output circuit in which the error operation codes are stored.
3. The memory system of claim 2 , wherein the error operation code output circuit sequentially outputs the error operation codes under the control of the memory controller, or randomly outputs the error operation codes.
4. The memory system of claim 1 ,
wherein the memory controller includes an error request table in which the one or more error requests are stored, and
wherein, when a normal request is received from the host, the memory controller compares the normal request to the one or more error requests stored in the error request table.
5. The memory system of claim 4 , wherein the memory controller compares the normal request to the one or more error requests before an operation for the normal request is performed.
6. The memory system of claim 4 , wherein, when it is determined that the normal request corresponds to any of the one or more of the error requests, the memory controller generates an error signal and outputs the error signal to the host.
7. The memory system of claim 1 , wherein the error test device further includes an error data output circuit in which error data including patterns showing how an error is generated are stored.
8. The memory system of claim 7 , wherein the error data output circuit sequentially outputs the error data under the control of the memory controller, or selectively or randomly outputs the error data.
9. A memory system comprising:
a memory device;
an error test device configured to generate an error operation code for performing an error operation of the memory device in response to a first request; and
a controller configured to test the memory device according to the error operation, determine whether the first request is an error-corresponding request when an error is detected during the error operation for the first request, and report an error corresponding to a second request without performing any operation for the second request when the second request is determined by the controller to be the error-corresponding request.