Non-volatile memory with silicided bit line contacts
View Patent ↗An approach to use silicided bit line contacts that do not short to the underlying substrate in memory devices. The approach provides for silicide formation in the bit line contact area, using a process that benefits from being self-aligned to the oxide-nitride-oxide (ONO) nitride edges. A further benefit of the approach is that the bit line contact implant and rapid temperature anneal process can be eliminated. This approach is applicable to embedded flash, integrating high density devices and advanced logic processes.
1. A memory device comprising:
a substrate comprising:
a plurality of bit lines, and
a plurality of body regions, wherein the pluralities of bit lines and body regions alternate along at least one axis;
a dielectric stack formed on at least one body region, the dielectric stack comprising an extended foot of a nitride layer of the dielectric stack; and
a gate layer formed on the dielectric stack.
2. The memory device of claim 1 , wherein at least two bit lines, the dielectric stack, and the gate layer form a charge-trapping field effect transistor (CT-FET).
3. The memory device of claim 1 , wherein the dielectric stack comprises a charge-trapping layer comprising a first charge-trapping region and a second charge-trapping region.
4. A method of forming a memory device, the method comprising:
disposing a plurality of bit lines within a substrate;
disposing a plurality of body regions within the substrate, the pluralities of bit lines and body regions substantially alternating;
disposing a dielectric stack on at least one body region, the dielectric stack comprising an extended foot of a nitride layer of the dielectric stack;
disposing a gate layer on the dielectric stack.
5. The method of forming a memory device of claim 4 , wherein disposing the dielectric stack comprises:
forming a tunnel dielectric on the at least one body region;
forming a charge-trapping layer on the tunnel dielectric; and
forming a top dielectric on the charge trapping layer.