System and method for localized logic simulation replay using emulated values
A computer executable system and method analyzes a circuit design to extract a small set of signals for value collection using an emulator system. The collected signals are for specific purpose checkers such as assertions or interactive testbenches that are hard to emulate. A synthesizable monitor block is generated and added to the emulation environment to collect the signal value changes during emulation. The collected values are then used in localized logic simulation to perform the tasks that the original checkers intent to accomplish. This system leverages fast emulation speed and flexible logic simulation capabilities to perform the intended checker tasks much faster than using logic simulation alone.
1. A method for replaying collect values on checkers, comprising:
receiving one or more design circuit signals used in checkers;
monitoring the one or more design circuit signals to collect one or more values by generating a counter in an emulator that counts a number of clocks for the monitored one or more signals;
identifying a change in value associated with the monitored one or more design circuit signals in the emulator;
writing the changed design circuit signal value and the associated clock count in the emulator in a signal value database; and
replaying the changed values from the signal value database using logic simulation on the checkers.
2. The method of claim 1 , wherein the one or more design circuit signals are extracted.
3. The method of claim 1 , wherein the checkers comprise assertions embedded in a design circuit or a testbench.
4. The method of claim 2 , further comprising:
during extraction of the one or more design circuit signals, analyzing a design circuit; and
distinguishing clock signals from data signals.
5. The method of claim 2 , further comprising: during replaying of the changed values, force signals not used by the checkers to constants.
6. A system for replaying collect values on checkers, comprising:
a memory having program instructions stored thereon; and
a processor configured to:
receive one or more design circuit signals used in checkers;
monitor the one or more design circuit signals to collect one or more values by generating a counter in an emulator that counts a number of clocks for the monitored one or more signals;
identify a change in value associated with the monitored one or more design circuit signals in the emulator;
write the changed design circuit signal value and the associated clock count in the emulator in a signal value database; and
replay the changed values from the signal value database using logic simulation on the checkers.
7. The system of claim 6 , wherein the one or more design circuit signals are extracted.
8. The system of claim 6 , wherein the checkers comprise assertions embedded in a design circuit or a testbench.
9. The system of claim 7 , wherein the processor is further configured to:
during extraction of the one or more design circuit signals, analyze a design circuit; and
distinguish clock signals from data signals.
10. The system of claim 7 , wherein the processor is further configured to:
during replaying of the changed values, force signals not used by the checkers to constants.
11. A non-transitory computer readable medium containing program instructions for causing a computer to perform the method of:
receiving one or more design circuit signals used in checkers;
monitoring the one or more design circuit signals to collect one or more values by generating a counter in an emulator that counts a number of clocks for the monitored one or more signals;
identifying a change in value associated with the monitored one or more design circuit signals in the emulator;
writing the changed design circuit signal value and the associated clock count in the emulator in a signal value database; and
replaying the changed values from the signal value database using logic simulation on the checkers.
12. The system of claim 11 , wherein the one or more design circuit signals are extracted.
13. The system of claim 11 , wherein the checkers comprise assertions embedded in a design circuit or a testbench.
14. The system of claim 12 , further comprising:
during extraction of the design circuit one or more signals, analyzing a design circuit; and
distinguishing clock signals from data signals.
15. The system of claim 12 , further comprising: during replaying of the changed values, force signals not used by the checkers to constants.