IP Library Granted Patent US 10,840,343
Granted Patent B1
US 10,840,343 · App. 16/671,549 · Granted Nov 17, 2020

Semiconductor structure for wide bandgap normally off MOSFET

Inventor: Chih-Jen Huang (Hsinchu, TW)
H01L29/408H01L29/2003H01L29/205H01L29/402H01L29/7786
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Quick Facts
Patent No.
US 10,840,343
App. No.
16/671,549
Granted
Nov 17, 2020
Kind
B1
Abstract

A semiconductor structure for a wide bandgap normally off MOSFET has a III-group nitride, a V-group nitride, or a high K material trapping layer disposed under a gate electrode. Through the FN tunneling effect or channel hot electron (CHE) effect, multiple electrons are trapped by the trapping layer and kept in the trapping layer. The electrons in the trapping layer deplete the two-dimensional electron gas (2DEG) below the trapping layer, and then the 2DEG below the gate electrode disappear.

Claims (23)

1. A semiconductor structure for a wide bandgap normally off MOSFET, comprising:

a substrate;

a buffer layer disposed on the substrate;

a barrier layer, which is disposed on the buffer layer and covers the buffer layer, wherein an interface between the buffer layer and the barrier layer has a two-dimensional electron gas (2DEG);

a source electrode;

a drain electrode; and

a gate electrode, wherein the source electrode and the drain electrode are disposed on the barrier layer, and the source electrode and the drain electrode are disposed on two opposite sides of the gate electrode to control a current flowing through the 2DEG;

wherein a III-group nitride, a V-group nitride, or a high K material trapping layer is disposed under the gate electrode, and multiple electrons are trapped by the trapping layer and kept in the trapping layer through a FN tunneling effect or channel hot electron effect (CHE); and the electrons in the trapping layer deplete the 2DEG below the trapping layer, which make the 2DEG below the gate electrode disappear so that the semiconductor structure forms a normally off MOSFET semiconductor structure.

2. The semiconductor structure according to claim 1 , further comprising:

an oxide layer disposed between the gate electrode and the trapping layer, and disposed between the trapping layer and the barrier layer.

3. The semiconductor structure according to claim 2 , wherein the oxide layer further covers both side surfaces of the trapping layer and the oxide layers.

4. The semiconductor structure according to claim 3 , wherein the buffer layer and the barrier layer are made of an III-V group material.

5. The semiconductor structure according to claim 4 , further comprising:

an isolation layer disposed between the gate electrode and the drain electrode and disposed on the barrier layer; and

a shielding gate disposed on the isolation layer and disposed between the gate electrode and the drain electrode.

6. The semiconductor structure according to claim 2 , wherein the electrons are injected into the trapping layer by FN tunneling effect with a voltage of the gate electrode is higher than or equal to 10 volts, and the source electrode and the drain electrode are grounded; or by channel hot electron effect with a gate voltage is higher than or equal to 5V, a source voltage is ground and a drain voltage is higher than or equal to 3V.

7. The semiconductor structure according to claim 1 , wherein when the trapping layer is the III-group nitride or the V-group nitride, the semiconductor structure further comprises:

a dielectric layer disposed between the gate electrode and the trapping layer, and disposed between the trapping layer and the barrier layer.

8. The semiconductor structure according to claim 7 , wherein the dielectric layer further covers both side surfaces of the trapping layer and the dielectric layers.

9. The semiconductor structure according to claim 8 , wherein the buffer layer and the barrier layer are made of an III-V group material.

10. The semiconductor structure according to claim 9 , further comprising:

an isolation layer disposed between the gate electrode and the drain electrode and disposed on the barrier layer; and

a shielding gate disposed on the isolation layer and disposed between the gate electrode and the drain electrode.