Efficient thermally-assisted switching
Disclosed are systems and methods for improving the performance of magnetoresistive random access memory (MRAM). MRAM is one of the promising potential replacements for existing DRAM and SRAM memory devices due to the many advantages of the technology which include non-volatility, fast read and write speeds, improved read and write endurance, and low operating voltage. In one embodiment, the processing rates or other activity of circuits nearby an MRAM cell subject to write operations can be increased to increase the temperature of the MRAM cell. The increased temperature lowers the write field required during a write operation, which in turn lowers the power requirement and the switching time of the MRAM cell.
1. A system, comprising:
an MRAM structure, comprising a plurality of MRAM cells;
a plurality of circuit elements, each configured to process one or more computing tasks at a processing rate;
a controller configured to:
determine MRAM cells subject to upcoming write operations;
determine one or more circuit elements, in the plurality of circuit elements and within a volume of thermal effect relative to the MRAM cells subject to write operations; and
increase processing rate of the one or more circuit elements within the volume of thermal effect.
2. The system of claim 1 , wherein the volume of thermal effect comprises a volume surrounding the MRAM cells subject to upcoming write operations, wherein thermal response of circuit elements within the volume of thermal effect influences thermal response of the MRAM cells within the volume of thermal effect.
3. The system of claim 1 , wherein the controller is further configured to increase the processing rate of the one or more circuit elements within the volume of thermal effect during write operations, or for a period of time starting before end of write operations, or from a predetermined period of time before end of write operations to a predetermined time after end of write operations.
4. The system of claim 1 , wherein the controller is further configured to increase the processing rate, one or more time steps before end of the write operations, wherein the one or more time steps are determined at least partly based on a predetermined time period, a dynamically-determined time period, a stochastically-determined time period, or a combination thereof.
5. The system of claim 1 , wherein the plurality of circuit elements comprise one or more of ALUs, control units, processor cores, registers, transistors, wire drivers, amplifiers, decoders, buses, gates, diodes, inverters and converters.
6. The system of claim 1 , wherein the volume of thermal effect comprises a cube of dimension of approximately 500 micrometers per side and centered around the MRAM cells subject to upcoming write operations.
7. The system of claim 1 , wherein the increase in processing rate is in an amount, such that thermal response of the one or more circuit elements within the volume of thermal effect, contributes to improving performance of write operations of the MRAM cells within the volume of thermal effect.
8. The system of claim 1 , wherein the MRAM structure comprises two-terminal MRAM, three-terminal MRAM, STT-MRAM, SOT-MRAM, two-terminal STT-MRAM, two-terminal SOT-MRAM, three-terminal STT-MRAM and three-terminal SOT-MRAM.
9. The system of claim 1 , wherein the MRAM cells are in a back-end-of-line (BEOL) metal layer and the one or more circuit elements within the volume of thermal effect comprise transistors in a layer underneath the BEOL layer.
10. The system of claim 1 , wherein the MRAM structure is part of a three-dimensional integrated circuit and the one or more circuit elements within the volume of thermal effect comprise transistors located along a vertical axis relative to the MRAM cells within the volume of thermal effect.
11. The system of claim 1 further comprising one or more microheaters within the volume of thermal effect and wherein the increase in processing rate is in an amount such that heat generated from the one or more microheaters and heat generated in the one or more circuit elements within the volume of thermal effect in combination improve write performance of the MRAM cells within the volume of thermal effect.
12. A method comprising:
determining MRAM cells subject to upcoming write operations;
determining a volume of thermal effect relative to the MRAM cells subject to write operations;
determining one or more circuit elements within the volume of thermal effect; and
increasing processing rate of the one or more circuit elements within the volume of thermal effect.
13. The method of claim 12 , wherein the volume of thermal effect comprises a volume surrounding the MRAM cells subject to upcoming write operations, wherein thermal response of circuit elements within the volume of thermal effect influences thermal response of the MRAM cells within the volume of thermal effect.
14. The method of claim 12 , wherein increasing the processing rate of the one or more circuit elements within the volume of thermal effect occurs during write operations, or occurs for a period of time starting before end of write operations, or occurs from a predetermined period of time before end of write operations to a predetermined time after end of write operations.
15. The method of claim 12 , wherein increasing the processing rate occurs one or more time steps before end of the write operations, wherein the one or more time steps are determined at least partly based on a predetermined time period, a dynamically-determined time period, a stochastically-determined time period, or a combination thereof.
16. The method of claim 12 , wherein increasing processing rate is in an amount, such that thermal response of the one or more circuit elements within the volume of thermal effect, contributes to improving performance of write operations of the MRAM cells within the volume of thermal effect.
17. The method of claim 12 , wherein the MRAM cells are part of an MRAM structure comprising two-terminal MRAM, three-terminal MRAM, STT-MRAM, SOT-MRAM, two-terminal STT-MRAM, two-terminal SOT-MRAM, three-terminal STT-MRAM and three-terminal SOT-MRAM.
18. The method of claim 12 , wherein the MRAM cells are in a back-end-of-line (BEOL) metal layer and the one or more circuit elements within the volume of thermal effect comprise transistors in a layer underneath the BEOL layer.
19. The method of claim 12 , wherein the MRAM cells are part of a three-dimensional integrated circuit and the one or more circuit elements within the volume of thermal effect comprise transistors positioned along a vertical axis relative to the MRAM cells within the volume of thermal effect.
20. The method of claim 12 , further comprising operating one or more microheaters within the volume of thermal effect and wherein the increase in processing rate is in an amount such that heat generated from the one or more microheaters and heat generated in the one or more circuit elements within the volume of thermal effect in combination improve write performance of MRAM cells within the volume of thermal effect.