Compute an optimized read voltage

1. A memory device, comprising:

an integrated circuit package enclosing the memory device; and

a plurality of groups of memory cells formed on at least one integrated circuit die;

wherein in response to a command identifying a group of memory cells within the plurality of groups, the memory device is configured to:

read the group of memory cells at a plurality of test voltages;

determine bit counts at the test voltages respectively, wherein each bit count at a test voltage identifies a number of memory cells in the group that, when read at the test voltage, provide a predetermined bit value;

compute count differences in the bit counts for pairs of adjacent voltages in the test voltages, wherein each count difference of a voltage interval between a pair of adjacent voltages in the test voltages is a difference between bit counts of the pair of adjacent voltages;

identify among the count differences, a first count difference that is no greater than at least two of the count differences, wherein the first count difference has a voltage interval that is not between two voltage intervals of the at least two of the count differences; and

determine a location of an optimized read voltage in the voltage interval of the first count difference, based on a ratio between the first count difference and a second count difference, the second count difference having a voltage interval that is closest to the voltage interval of the first count difference in the at least two of the count differences.

2. The memory device of claim 1 , wherein the location of the optimized read voltage is selected from a plurality of candidates on the voltage interval of the first count difference.

3. The memory device of claim 2 , wherein the plurality of candidates is evenly distributed on the voltage interval of the first count difference.

4. The memory device of claim 3 , wherein the plurality of candidates corresponds to a logarithmic distribution of the ratio between the first count difference and the second count difference.

5. The memory device of claim 2 , wherein the memory device is configured to:

scale at least one of the first count difference and the second count difference to generate a scaled version; and

compare to the scaled version to select the location of the optimized read voltage from a plurality of candidates.

6. The memory device of claim 5 , wherein the memory device is configured to scale the at least one of the first count difference and the second count difference by a bit shifting operation.

7. The memory device of claim 6 , wherein the memory device is configured to:

shift a first one of the first count difference and the second count difference repeatedly to generate a series of scaled versions;

compare the series of scaled versions, one after another, to a second one of the first count difference and the second count difference; and

adjust the location of the optimized read voltage by a predetermined increment in response to any of the series of scaled versions meeting a predetermined relation in comparing to the second one of the first count difference and the second count difference.

8. The memory device of claim 7 , wherein the predetermined increment is one fifth of the voltage interval of the first count difference.

9. A method, comprising:

reading a group of memory cells in a memory device at a plurality of test voltages;

determining bit counts at the test voltages respectively, wherein each bit count at a test voltage identifies a number of memory cells in the group that, when read at the test voltage, provide a predetermined bit value;

computing count differences in the bit counts for pairs of adjacent voltages in the test voltages, wherein each count difference of a voltage interval between a pair of adjacent voltages in the test voltages is a difference between bit counts of the pair of adjacent voltages;

identifying among the count differences, a first count difference that is no greater than at least two of the count differences, wherein the first count difference has a voltage interval that is not between two voltage intervals of the at least two of the count differences; and

determining a location of an optimized read voltage in the voltage interval of the first count difference, based on a ratio between the first count difference and a second count difference, the second count difference having a voltage interval that is closest to the voltage interval of the first count difference in the at least two of the count differences.

10. The method of claim 9 , wherein the location of the optimized read voltage is determined based on mapping a logarithmic scale of the ratio between the first count difference and the second count difference to a linear distribution for the location of the optimized read voltage in the voltage interval of the first count difference.

11. The method of claim 10 , wherein the location of an optimized read voltage is determined without performing floating point number operations.

12. The method of claim 10 , further comprising:

generating a plurality of scaled versions of at least one of the first count difference and the second count difference; and

comparing the scaled versions to determine the location of the optimized read voltage.

13. The method of claim 12 , wherein the scaled versions are generated by a shifting operation.

14. The method of claim 12 , wherein the scaled versions are scaled by factors of two to power of predetermined numbers.

15. The method of claim 14 , wherein the scaled versions are generated by repeatedly scaling by a factor of two.

16. The method of claim 15 , wherein the determining of the location of the optimized read voltage is based on comparing a non-scaled one of the first count difference and the second count difference to the scaled versions.

17. The method of claim 15 , wherein the determining of the location of the optimized read voltage includes:

setting the location initially at one of test voltages corresponding to the voltage interval of the first count difference; and

adjusting the location by a predetermined amount in response to a determination that a predetermined relation is satisfied between:

the non-scaled one of the first count difference and the second count difference, and

a scaled version in the plurality of scaled versions.

18. A memory sub-system, comprising:

a processing device; and

at least one memory device, the memory device having a group of memory cells formed on an integrated circuit die;

wherein the processing device is configured to transmit, to the memory device, a command with an address identifying the group of memory cells;

wherein in response to the command, the memory device is configured to:

read the group of memory cells at a plurality of test voltages;

determine bit counts at the test voltages respectively, wherein each bit count at a test voltage identifies a number of memory cells in the group that, when read at the test voltage, provide a predetermined bit value;

compute count differences in the bit counts for pairs of adjacent voltages in the test voltages, wherein each count difference of a voltage interval between a pair of adjacent voltages in the test voltages is a difference between bit counts of the pair of adjacent voltages;

compare the count differences;

identify among the count differences, a first count difference that is no greater than at least two of the count differences, wherein the first count difference has a voltage interval that is not between two voltage intervals of the at least two of the count differences; and

determine a location of an optimized read voltage in the voltage interval of the first count difference, based on a ratio between the first count difference and a second count difference, the second count difference having a voltage interval that is closest to the voltage interval of the first count difference in the at least two of the count differences.

19. The memory sub-system of claim 18 , wherein the location is determined based on mapping a logarithmic scale of the ratio to a linear distribution of the location on the voltage interval of the first count difference.

20. The memory sub-system of claim 19 , wherein memory device is configured to:

set the location at a test voltage that separates the voltage interval of the first count difference and the voltage interval of the second count difference;

compare the first count difference and the second count difference;

move the location away from the voltage interval of the second count difference by a predetermined amount in response to a determination that the first count difference is smaller than the second count difference;

scale the second count difference by a factor of two to generate a scaled version of the second count difference;

compare the first count difference and the scale version of the second count difference;

move the location further away from the voltage interval of the second count difference by the predetermined amount in response to a determination that the first count difference is smaller than the scaled version of the second count difference;

scale the scaled version of the second count difference by a factor of two to generate a further scaled version of the second count difference;

compare the first count difference and the further scale version of the second count difference; and

move the location even further away from the voltage interval of the second count difference by the predetermined amount in response to a determination that the first count difference is smaller than the further scaled version of the second count difference.